Mapping search method and device for cache memory and main memory

Abstract

A method and device for mapping lookup between a cache and a main memory; an optical comparator realizes a logical operation relationship xor by utilizing the above relation of a micro ring size in an optical field instead of negating a control signal A and an input signal B in an electric field; because of the parallelism of light, the optical comparator is capable of parallelism calculation and has small delay, and can be used to search the cache for the position of the data required by the CPU; and compared with a logic circuit implementing fully-associative mapping in the prior art, the logic circuit of the fully-associative mapping implemented by the optical comparator has a simpler structure, and the comparison delay does not increase with the increase of the number of compared bits.

Description

technical field [0001] The embodiment of the present invention relates to computer technology, in particular to a method and device for mapping and searching a cache memory and a main memory. Background technique [0002] A computer storage system refers to a computer system consisting of various storage devices for storing programs and data, control components, and equipment (hardware) and algorithms (software) for managing information scheduling. [0003] A storage system in an existing computer includes a central processing unit (Central Processing Unit, referred to as CPU), a high-speed cache memory (Cache, referred to as a cache), a main memory (Main memory, referred to as a main memory) and an auxiliary memory (auxiliary storage). structured as figure 1 As shown, specifically, information can be directly exchanged between the CPU and the main memory, but since the speed of the main memory cannot meet the access requirements of the CPU, a cache is added between the two...

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Problems solved by technology

[0004] Among them, the fully associative mapping allows each block in the main memory to be mapped to any block in the cache, such as figure 2 As shown, the main memory and the cache are divided into data blocks of the same size. A data block of the main memory can be loaded into any space in the cache. This mapping method can replace any old word from the full cache. block, because any data block in the main memory can be loaded into any space in the cache, so the storage space utilization rate of the cache is high. When the CPU needs to access data, the Cache hit rate is relatively high. However, when accessing data blocks At this time, the cache must compare the main memory word block tag of the data block with all the tags in the cache each time before judging whether the required data block is in the cache. Using this address mapping method, the number of bits and bits that need to be compared The number of times is large, which leads to the disadvantages of complex logic circuit design and increased delay

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