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Novel compact, efficient and fast on-chip network router based on network coding

A network coding and network-on-chip technology, applied in the field of network-on-chip routers, can solve problems such as the lack of targeted improvements in the structure and performance characteristics of the on-chip network, the lack of experimental data on delay and power consumption, etc., so as to improve performance and reduce power consumption. Effect

Active Publication Date: 2016-08-17
GUANGDONG UNIV OF TECH
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  • Claims
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Problems solved by technology

In addition, most of these documents are based on rough theoretical evaluation of network coding, lacking accurate delay and power consumption experimental data in the actual circuit environment, optimization algorithms are also based on existing network coding theory, and have not targeted the structure and performance characteristics of the network on chip. However, it is difficult to conduct a comprehensive and comprehensive research and evaluation on the role of network coding in promoting network-on-chip.

Method used

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  • Novel compact, efficient and fast on-chip network router based on network coding
  • Novel compact, efficient and fast on-chip network router based on network coding
  • Novel compact, efficient and fast on-chip network router based on network coding

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Embodiment

[0034] The proposal of network coding is in the traditional macro network environment (such as wireless sensor network, computer network, etc.), the routers of these networks have strong processing and storage functions, while supporting the routing function, it can be enough to cope with network coding extra work. Moreover, compared to the delay and power consumption of network channel transmission, the additional delay and power consumption consumed by network coding are small or negligible. However, the network-on-chip is a micro-network with extremely strict requirements on speed and hardware resources. Its processing and caching capabilities are very weak, and it is impossible to consume too many extra hardware and energy resources to support network coding.

[0035] Figure 1(a) is a typical butterfly network coding structure: s1 and s2 are two multicast source nodes; d1 and d2 are two multicast destination nodes; is is an intermediate source node, which is a router, It ...

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Abstract

The invention discloses a novel compact, efficient and fast on-chip network router based on network coding. The router comprises P ways of input and output channels, wherein each input channel is provided with v virtual channels; each input channel is provided with one routing logic and a virtual channel allocator which are respectively responsible for a routing direction of data transmission and allocation of the virtual channels; the virtual channel allocator is also connected to a switch allocator; the switch allocator is responsible for allocating crossbars to the P ways of input channels, so that arbitration of one output channel is simultaneously requested by multiple input channels; network coding modules NCU are also arranged between the P ways of input channels and the cross switches; the output of flits of the virtual channel passes through a simple coding selection circuit, the NCU carries out coding operations on the input which conforms to the conditions, after the coded flits are arbitrated by the switch allocator, the flits are sent to the crossbars. The on-chip network router supports a transmission mode with the flits as a unit, the real-time coding is realized and the additional hardware and power consumption can be effectively reduced.

Description

technical field [0001] The invention relates to the research field of network routers, in particular to a novel compact, efficient and fast on-chip network router based on network coding. Background technique [0002] With the continuous development of semiconductor technology, the number of transistors accommodated in a single chip continues to increase, and integrated circuits have entered a multi-core (multiple-core) or many-core (many-core) era. The cores are connected together by Network-on-Chip or NoC, and the overall performance of the chip is improved through parallel computing. At present, many-core chips have achieved a large number of commercial applications. For example: Intel 48-core cloud computer single-chip cloud computer "single-chip cloudcomputer" and Tilera 72-core TILE-Gx72 single chip. These chips are widely used in supercomputing, cloud computing, big data and other systems. [0003] As the scale and parallelism of many-core chips continue to increas...

Claims

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Application Information

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IPC IPC(8): H04L12/771H04L12/931H04L12/26H04L1/00H04L45/60
CPCH04L1/0076H04L43/50H04L45/60H04L49/109
Inventor 刘怡俊谢建群
Owner GUANGDONG UNIV OF TECH
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