A Method of Low-Order Interleaving for Large-capacity Data Using FPGA

A data and cross-module technology, applied in the field of communication, to achieve the effect of reduced demand and strong access capability

Active Publication Date: 2018-10-19
TOEC TECH
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Problems solved by technology

[0003] However, in some fields, it is necessary to screen and filter a large amount of data, cross-converge, extract useful information from it for processing, and the increasingly large amount of data carried on the optical fiber has a great impact on the access capacity of information screening equipment. and cross-processing capabilities present new challenges

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  • A Method of Low-Order Interleaving for Large-capacity Data Using FPGA
  • A Method of Low-Order Interleaving for Large-capacity Data Using FPGA
  • A Method of Low-Order Interleaving for Large-capacity Data Using FPGA

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Embodiment Construction

[0024] The present invention will be further described below in conjunction with accompanying drawing:

[0025] The working principle of FPGA (Field Programmable Gate Array) chip: refer to figure 1 , the chip function is divided into seven functional modules: data receiving module, pointer interpretation and adjustment module, multiframe information binding module, low-level crossover module, multiframe alignment module, processor interface module and data transmission module. Among them, the four modules of pointer interpretation and adjustment, multiframe information binding, low-level crossover, and multiframe alignment are the core modules in this solution, reflecting the idea of ​​crossover first and then multiframe alignment. The three modules of data receiving, processor interface and data sending are conventional modules for processing SDH data, and the above seven modules complete the functions of the entire chip.

[0026] refer to figure 2 , The data receiving mod...

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Abstract

The invention discloses a method for adopting an FPGA to carry out low order cross connect on large volume data. The method changes a conventional way that multi-frame alignment and cross are needed when the low order cross connect is carried in a synchronous digital system, aims at application characteristics of large input bandwidth and small output bandwidth of an information screening field, and adopts a way of cross, convergence and multi-frame alignment to operate after the accessed large volume data is processed through data reception, pointer interpreter and adjustment and multi-frame information binding modules. According to the method, the requirements of design for internal cache of a chip can be greatly reduced, the data access with the larger bandwidth can be realized, and the stronger access, cross and data handling capacity can be provided. The conventional method only completes the low order capacity of 20G*20G, the method can complete the low order capacity of 80G*20G without any additional external cache, and the method has remarkable advantages in the aspects of hardware cost, access capacity and operability.

Description

technical field [0001] The invention relates to the field of communication, information identification and screening, and in particular to pointer interpretation and adjustment technology, low-order crossover technology, screening and recombination technology of Synchronous Digital Hierarchy (SDH). In particular, it relates to a method for performing low-order interleaving on large-capacity data by using FPGA. Background technique [0002] Due to the advantages of large transmission capacity, low loss, light weight, small size, strong anti-electromagnetic interference and good confidentiality, optical fiber communication has more and more applications in communication. Not only the backbone network and the metropolitan area network all use optical fiber transmission , and the access network generally uses optical fiber to achieve aggregation. At present, the data carried on the optical fiber can be described as vast. [0003] However, in some fields, it is necessary to scr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/16
CPCH04J3/1611
Inventor 李斌郝书宁张晓峰汪洋袁雷张东王尧张亚望
Owner TOEC TECH
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