Calculation by hardware method of power loss for processing devices with non-volatile logic memory

A volatile storage, non-volatile technology, applied in the input/output process of data processing, digital data processing components, calculations, etc., can solve the problems of time delay, battery resource dissipation, etc.

Active Publication Date: 2021-08-10
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition to the time delay, this restart process further drains applicable battery resources
This is a painful process for customers using such computing or processing equipment experiencing interruptible power and / or using deep low power modes

Method used

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  • Calculation by hardware method of power loss for processing devices with non-volatile logic memory
  • Calculation by hardware method of power loss for processing devices with non-volatile logic memory
  • Calculation by hardware method of power loss for processing devices with non-volatile logic memory

Examples

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Embodiment Construction

[0016] Turning now to the attached drawings, especially figure 1 , an example computing device arrangement 100 compatible with many of these teachings will now be described. The computing device 100 includes a central processing unit ("CPU") 105, a first non-volatile memory 107, a volatile general and status register memory 110, a second non-volatile memory 115, and a plurality of peripheral devices or device modules 120. . The first nonvolatile memory 107 is connected to store software-related information such as programs and variable data. Memory 110 and configuration registers 125 are volatile storage elements configured to store configuration profiles for the current active settings of computing device 100 or peripheral devices 120 associated with computing device 100. file data. Memory 110 storing data for CPU 105 may be embedded within CPU 105 , or memory 110 may be separate from and associated with CPU 105 . The energy storage unit 130 is connected to provide power ...

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PUM

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Abstract

The present disclosure relates to computing by power-loss hardware methods for processing devices with non-volatile logic memory. Computing device means (100) facilitates use of a deep low power mode comprising storing data from a volatile storage element (110, 125) of the device (100) in a non-volatile The CPU (105) of the device (100) is powered down by a hardware-implemented process in the persistent memory (115). The hardware-based power management unit (140) control includes interrupting the normal processing sequence of the CPU (105) and triggering the process of storing data in the non-volatile memory (115). In response to a wake event, the device (100) is triggered to restore data stored in the non-volatile memory (115) to the volatile memory (110) prior to performing the wake-up procedure for the CPU (105) from the low power mode , 125). The device (100) includes a power storage element (130), such as a capacitor, that maintains sufficient energy to perform non-volatile data storage tasks before entering a low power mode.

Description

[0001] related application [0002] This application claims the benefit of US Provisional Patent Application No. 62 / 272,473, filed December 29, 2015, the contents of which are hereby incorporated by reference in their entirety. technical field [0003] The present invention relates generally to processing devices with non-volatile memory, and in particular to power-loss operation for such processing devices. Background technique [0004] Electronic devices continue to face performance pressures including providing increased computing power and providing varying control performance. This performance pressure also includes the need for ever-increasing capacity to extend battery life or generally improve the power efficiency of computing device operation. Accordingly, various types of computing devices include different ways of entering low power modes that allow a given device to use less power. Low power modes typically include disabling the use of various features or power...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/3234G06F1/3215G06F12/16
CPCG06F1/3225G06F1/3275G06F12/16G06F1/3293G06F3/061G06F3/0656G06F3/0634G06F11/07G06F3/0625G06F3/0655G06F3/0688G06F1/3206G06F1/3287Y02D10/00Y02D30/50
Inventor M·茨韦格S·C·巴特林S·汉纳
Owner TEXAS INSTR INC
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