vlan frame processing method, device and server
A frame processing and register technology, applied in the field of communication, can solve the problems of high cost and complex control, achieve the effect of simple read and write control, reduce hardware and control maintenance costs
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Embodiment 1
[0033] In the Vlan frame processing method provided in this embodiment, register unit 0, register unit 1, . . . , register unit i, . Then after obtaining the Vlan frame that contains the Vlan tag, it is parsed, and the data obtained by parsing takes 1 byte as the step size and 1 clock as the writing cycle, and writes the register unit 0 in sequence, and at each Clock cycle, the data in the previous register unit is written into the latter register unit; when data is written in the register unit n, judge whether the data in the register unit n is Vlan label data, if not, from the register unit n Read data, and continue to write data in the previous register unit to the next register unit; otherwise, read data from register unit 0 in each subsequent clock cycle, and stop writing data in the previous register unit For the latter register unit, the present invention can also effectively strip the VlanTag data in the Vlan frame by using n+1 register units, without using FIFO logic ...
Embodiment 2
[0048] This embodiment provides a kind of Vlan frame processing device, this device is aimed at the Vlan frame that contains VlanTag and VlanTag length is n bytes, register unit 0, register unit 1, ..., register unit i, ... register unit connected in sequence are set n. Then after obtaining the Vlan frame that contains the Vlan tag, it is parsed, and the data obtained by parsing takes 1 byte as the step size and 1 clock as the writing cycle, and writes the register unit 0 in sequence, and at each Clock cycle, the data in the previous register unit is written into the latter register unit; when data is written in the register unit n, judge whether the data in the register unit n is Vlan label data, if not, from the register unit n Read data, and continue to write data in the previous register unit to the next register unit; otherwise, read data from register unit 0 in each subsequent clock cycle, and stop writing data in the previous register unit The latter register unit, so ...
Embodiment 3
[0061] In order to facilitate the understanding of the present invention, this embodiment takes the Vlan tag data contained in the Vlan frame as an example with a length of 4 bytes and specific data as 0x81 0x00 0x0a 0xbc. For the structure of the Vlan frame, see Figure 5 As shown, the Vlan tag 802.1Q VLAN Tag in the Vlan frame occupies 4 bytes. Assume that all the data output by parsing the Vlan frame is the input data: 0x01 0x02 0x03 0x04 0x05 0x81 0x00 0x0a 0xbc 0x06 0x07
[0062] The inserted Vlan tag data is: 0x81 0x00 0x0a 0xbc,
[0063] The output data after processing is: 0x01 0x02 0x03 0x04 0x05 0x06 0x07;
[0064] Set 5 registers, which are numbered 0, 1, 2, 3, 4 in sequence, among which 1, 2, 3, 4 registers are respectively written into the four bytes of the Vlan label, Figure 6 Indicates the control of each register in the FPGA logic, Figure 7 The arrow in the figure indicates the direction of data transmission. Registers 0, 1, 2, 3, and 4 are pipelined, tha...
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