File transmission system of protocol reconfigurable 10 Gigabit communication

A file transmission, 10G technology, applied in the transmission system, electrical components, etc., to achieve the effect of simple circuit logic structure, good maintainability, and stable performance

Pending Publication Date: 2019-02-15
EAST CHINA NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, 10G network data communication is required between enterprise servers, and in order to ensure its reliability, the

Method used

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  • File transmission system of protocol reconfigurable 10 Gigabit communication
  • File transmission system of protocol reconfigurable 10 Gigabit communication
  • File transmission system of protocol reconfigurable 10 Gigabit communication

Examples

Experimental program
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Embodiment 1

[0025] See attached figure 2 , need two when the present invention works, and one of them and A mainframe server 9 are sending end , and the other is connected to host B server 10 as the receiving end , using 10 Gigabit Ethernet 91 to connect the sending end and the receiver , to carry out 10 Gigabit network data communication.

[0026] The present invention works like this: sending end workflow, A host server 9 inserts the PCIE data control module 61 by the PCIE data receiving engine 62 with the form of TLP packet, and the PCIE data that the PCIE data control module 61 will receive After being shaped into 128bit AXI Stream data stream, it is connected to the output data cache module 32 for caching and bit width transformation, and matches the rate of data entering and leaving the network data cache module 32, and the data stream after caching and bit width transformation is input to the packet header splicing module once 41 and the calculation module 42, perform oper...

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Abstract

The invention discloses a file transmission system of protocol reconfigurable 10 Gigabit communication. The system is characterized by being composed of an input interface module, an unloading and parsing module, a caching module, a reconfiguration module, an output module, an interface conversion module, a clock module and a power supply module, wherein the input interface module is orderly connected with the unloading and parsing module, the caching module, the reconfiguration module and the output module; the unloading and parsing module is connected with the output module; the caching module is connected with the interface conversion module; and the clock module and the power supply module respectively provide a clock and a power supply for each functional module. Compared with the prior art, the system provided by the invention has simple circuit logic structures and steady performance, improves processor efficiency and working efficiency of a host CPU when a server performs 10Gigabit data communication, well solves a problem that network protocol processing load is relatively high when 10 Gigabit network data communication is needed among the servers, and has excellent maintainability.

Description

technical field [0001] The invention relates to the technical field of network communication and data server, in particular to a file transmission system with protocol reconfigurable 10 Gigabit communication. Background technique [0002] The speed of network communication is developing rapidly in today's era, from 100M, 1000M to 10M, and the traffic of network data has also increased greatly. However, network communication is carried out under the network protocol standard. In order to comply with the standard, processing the entire network protocol stack requires a lot of server resources, especially the TCP / IP protocol stack under 10G network traffic, which will reduce the speed and efficiency of the server to process core data. Greatly reduced. In order to reduce the server's pressure on the network protocol stack processing, a concept of a TCP protocol stack load reduction engine is proposed. The TCP / IP protocol stack is built on the core CPU off-chip hardware logic ci...

Claims

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Application Information

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IPC IPC(8): H04L29/06H04L29/08
CPCH04L67/06H04L69/16
Inventor 刘一清吴惑石华
Owner EAST CHINA NORMAL UNIVERSITY
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