Manufacturing method of semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. Firstly, a first dummy gate structure and a second dummy gate structure with different top surface heights are formed in the first region and the second region, and then the top surface is formed by using an interlayer dielectric layer. The first dummy gate structure with a relatively low height is protected, and the second dummy gate structure is replaced with a second metal gate structure, and then the height of the top surface of the second dummy gate structure is adjusted again through the chemical mechanical planarization process. lower until the first dummy gate structure is exposed, thus the first dummy gate structure can be replaced by the first metal gate structure, and the method of the present invention avoids the original problem of forming layers with different work functions The photolithography process and the etching process enable the formation processes of the first metal gate structure and the second metal gate structure to be independent of each other, without causing additional process damage to the semiconductor substrate area where each other is located, and improving the final manufacturing process. performance of the resulting semiconductor device.

Description

Technical field [0001] The present invention relates to the field of manufacturing integrated circuit technology, particularly to a method of manufacturing a semiconductor device. Background technique [0002] A FinFET (fin field effect transistor) devices, a semiconductor device is advanced 22nm technology node and below is used, which can effectively control the device by scaling down the short channel effect caused insurmountable, it can achieve reduction of the gate device pole width, which structure generally comprises a fin protruding from the surface of the semiconductor substrate (the fin), covering the portion of the fin (channel region) of the top surface and / or on the sidewalls of the gate stack structure and the gate is located source and drain regions in the fins on both sides of the stack structure, the planar MOSFET (metal oxide silicon semiconductor field effect transistor) devices compared, a FinFET device can be kept low in off current while increasing the dri...

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