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FPGA, dual-screen TV, boot display method, device and medium

A technology to display and image, applied in FPGA, equipment and media, power-on display method, dual-screen TV field, can solve problems such as image signal instability, blurred screen, black screen, etc., and achieve the effect of avoiding black screen problems

Active Publication Date: 2022-05-27
青岛信芯微电子科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Embodiments of the present invention provide an FPGA, a dual-screen TV, a boot display method, device, and medium to solve the problems of black screen and blurred screen when the stacked TV is turned on caused by the instability of the image signal in the existing VBO format.

Method used

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  • FPGA, dual-screen TV, boot display method, device and medium
  • FPGA, dual-screen TV, boot display method, device and medium
  • FPGA, dual-screen TV, boot display method, device and medium

Examples

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Effect test

Embodiment 1

[0061] figure 1 A schematic structural diagram of an FPGA provided by an embodiment of the present invention, such as figure 1 As shown, the FPGA 100 includes: a graphic card generation module 101, an output TX module 102 and a VBO-RX module 103;

[0062] The VBO-RX module 103 is used to send the first signal to the MCU 200 when it does not receive a stable image signal;

[0063] The image card generation module 101 is configured to receive a start command sent by the MCU 200 after receiving the first signal, and generate a LOGO image to be displayed on the lower panel according to the image card information of the pre-saved LOGO image, wherein, The card information includes light transmittance information;

[0064] The output end TX module 102 is configured to receive the LOGO image to be displayed on the lower panel, and send the LOGO image to the lower panel for display.

[0065] In this embodiment of the present invention, the FPGA 100 includes a graphic card generation...

Embodiment 2

[0084] In order to display the LOGO image more accurately, on the basis of the above embodiment, in this embodiment of the present invention, the image card generation module 101 includes:

[0085] The obtaining sub-module 1011 is configured to obtain the image card information of the pre-saved LOGO image after receiving the startup command sent by the MCU 200, and send the image card information to the timing control sub-module 1013;

[0086] The timing generation sub-module 1012 is configured to generate a first timing signal for controlling the display of the LOGO image according to the received clock signal sent by the MCU, and send the first timing signal to the timing control sub-module 1013 ;

[0087]The timing control sub-module 1013 is configured to determine each target moment for displaying the LOGO image according to the received first timing signal, and at each target moment, the lower panel generated according to the image card information The LOGO image to be d...

Embodiment 3

[0102] In order to establish a stable connection between the VBO-RX module 103 and the image signal, on the basis of the above-mentioned embodiments, in this embodiment of the present invention, the VBO-RX module 103 is also used for receiving the first data sent by the MCU 200. When there is a control signal, the VBO-RX module 103 is controlled to reset, wherein the first control signal is sent by the MCU after receiving the first signal.

[0103] In this embodiment of the present invention, the VBO-RX module 103 resets after receiving the first control signal sent by the MCU 200 , where the first control signal is generated after the MCU 200 receives the first signal.

[0104] In the embodiment of the present invention, after the FPGA 100 loads the netlist file, the MCU 200 configures parameters for the VBO-RX module 103 in the FPGA 100, and after a reset, the VBO-RX module 103 starts to establish a connection with the image signal.

[0105] In order to reset itself when the...

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Abstract

The present invention discloses an FPGA, a double-screen TV, a start-up display method, equipment and a medium. The VBO-RX module in the FPGA is used to send a first signal to the MCU when it does not receive a stable image signal; This graph card generating module is used to receive the startup command sent by the MCU after receiving the first signal, and generates the LOGO image to be displayed on the lower panel according to the graph card information of the pre-saved LOGO image; the output terminal TX module, It is used to receive the LOGO image to be displayed on the lower panel, and send the LOGO image to the lower panel for display. Since the present invention does not receive a stable image signal when the VBO-RX module, the MCU controls the map card generation module to start, and generates a LOGO image according to the pre-saved map card information, thereby providing stable connection between the image signal and the VBO-RX module. Time buffering to avoid black screen or blurred screen when booting.

Description

technical field [0001] The invention relates to the technical field of stacked-screen TVs, and in particular, to an FPGA, a dual-screen TV, a start-up display method, a device and a medium. Background technique [0002] Existing TVs are increasingly unable to meet the user's requirements for image display clarity and color reproduction. In order to meet the user's requirements, a multi-screen TV has appeared. [0003] Stacked screen refers to a stacked screen display solution using two upper and lower panels. The upper panel is a color screen, which focuses on fine control of color, which can realize the importance of restoring color; the lower panel is a black and white screen, and the black and white screen focuses on fine dimming. Renders high contrast and darkfield details. In the prior art, a logic board (Timing Controller, TCON) is used to control the upper panel, and a field programmable gate array (Field Programmable Gate Array, FPGA) is used to control the lower pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N21/426H04N21/443H04N21/431
CPCH04N21/426H04N21/443H04N21/4312
Inventor 夏建龙王伟徐卫
Owner 青岛信芯微电子科技股份有限公司
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