FPGA, double-screen television, startup display method, equipment and medium

A technology to be displayed and image, applied in electrical components, image communication, selective content distribution, etc., can solve problems such as blurry screen, unstable image signal, black screen, etc.

Active Publication Date: 2020-09-29
青岛信芯微电子科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Embodiments of the present invention provide an FPGA, a dual-screen TV, a boot display method, device, and medium to solve the problems of black screen and blurred screen when the stacked TV is turned on caused by the instability of the image signal in the existing VBO format.

Method used

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  • FPGA, double-screen television, startup display method, equipment and medium
  • FPGA, double-screen television, startup display method, equipment and medium
  • FPGA, double-screen television, startup display method, equipment and medium

Examples

Experimental program
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Effect test

Embodiment 1

[0061] figure 1 A schematic structural diagram of an FPGA provided by an embodiment of the present invention, such as figure 1 As shown, the FPGA100 includes: a graphics card generation module 101, an output TX module 102 and a VBO-RX module 103;

[0062] The VBO-RX module 103 is configured to send a first signal to the MCU200 when it does not receive a stable image signal;

[0063] The graphic card generation module 101 is configured to receive the startup command sent by the MCU200 after receiving the first signal, and generate the LOGO image to be displayed on the lower panel according to the graphic card information of the pre-saved LOGO image, wherein, Chart information includes light transmittance information;

[0064] The output terminal TX module 102 is used to receive the LOGO image to be displayed on the lower panel, and send the LOGO image to the lower panel for display.

[0065] In the embodiment of the present invention, the FPGA 100 includes a graphic card gen...

Embodiment 2

[0084] In order to display the LOGO image more accurately, on the basis of the foregoing embodiments, in the embodiment of the present invention, the map generation module 101 includes:

[0085] The obtaining submodule 1011 is configured to obtain the graphic card information of the pre-saved LOGO image after receiving the startup command sent by the MCU200, and send the graphic card information to the timing control submodule 1013;

[0086] Timing generation sub-module 1012, configured to generate a first timing signal for controlling the display of the LOGO image according to the received clock signal sent by the MCU, and send the first timing signal to the timing control sub-module 1013 ;

[0087]The timing control sub-module 1013 is configured to determine each target moment for displaying the LOGO image according to the received first timing signal, and at each target moment, the lower panel generated according to the graphic card information will The LOGO image to be di...

Embodiment 3

[0102] In order to establish a stable connection between the VBO-RX module 103 and the image signal, on the basis of the above-mentioned embodiments, in the embodiment of the present invention, the VBO-RX module 103 is also used to When a control signal is received, the VBO-RX module 103 is controlled to reset, wherein the first control signal is sent by the MCU after receiving the first signal.

[0103] In the embodiment of the present invention, the VBO-RX module 103 resets after receiving the first control signal sent by the MCU200, wherein the first control signal is generated by the MCU200 after receiving the first signal.

[0104] In the embodiment of the present invention, after the FPGA100 finishes loading the netlist file, the MCU200 configures parameters for the VBO-RX module 103 in the FPGA100, and after a reset, the VBO-RX module 103 starts to establish a connection with the image signal.

[0105] In order to reset itself when the VBO-RX module 103 determines that ...

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Abstract

The invention discloses an FPGA (Field Programmable Gate Array), a double-screen television, a startup display method, startup display equipment and a medium. A VBO-RX module in the FPGA is used for sending a first signal to an MCU (Microprogrammed Control Unit) when the VBO-RX module does not receive a stable image signal; a graphic card generation module is used for receiving a starting commandsent by the MCU after receiving the first signal, and generating a LOGO image to be displayed on a lower panel according to graphic card information of the pre-stored LOGO image; and an output end TXmodule is used for receiving a LOGO image to be displayed on the lower panel and sending the LOGO image to the lower panel for display. According to the invention, when the VBO-RX module does not receive a stable image signal, the VBO-RX module is switched to the VBO-RX module; the MCU controls the graphic card generation module to start, and generates the LOGO image according to the pre-stored graphic card information, thereby providing time buffer for stable connection between the image signal and the VBO-RX module, and avoiding the problem of black screen or blurred screen during startup display.

Description

technical field [0001] The present invention relates to the technical field of multi-screen TVs, in particular to an FPGA, a double-screen TV, a power-on display method, equipment and media. Background technique [0002] Existing TVs are increasingly unable to meet users' requirements for image display clarity and color reproduction. In order to meet users' requirements, a multi-screen TV has emerged. [0003] Stacked screen refers to the stacked screen display scheme using two upper and lower panels. The upper panel is a color screen, which focuses on the fine control of colors, which can realize the emphasis on restoring colors; the lower panel is a black and white screen, which focuses on fine dimming, which can Presents high contrast and dark field details. In the prior art, a logic board (Timing Controller, TCON) is used to control the upper panel, and a Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is used to control the lower panel. [0004] Af...

Claims

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Application Information

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IPC IPC(8): H04N21/426H04N21/443H04N21/431
CPCH04N21/426H04N21/443H04N21/4312
Inventor 夏建龙王伟徐卫
Owner 青岛信芯微电子科技股份有限公司
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