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Division scheduling-based heuristic processor division method and system for DAG task and storage medium

A processor and heuristic technology, applied in the field of data processing, can solve problems such as unclear

Active Publication Date: 2021-03-09
HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL
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  • Claims
  • Application Information

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Problems solved by technology

However, under partition fixed priority scheduling, how to allocate subtasks of DAG tasks to reduce worst-case response time and improve task schedulability is still unclear

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  • Division scheduling-based heuristic processor division method and system for DAG task and storage medium
  • Division scheduling-based heuristic processor division method and system for DAG task and storage medium
  • Division scheduling-based heuristic processor division method and system for DAG task and storage medium

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Embodiment Construction

[0060] The invention discloses a heuristic processor division method of DAG tasks based on division scheduling. The invention studies the processor allocation problem of fixed priority division scheduling of parallel DAG tasks on multi-processors. Since the problem has been shown to be NP-hard [15], one cannot hope to find an optimal processor allocation strategy in polynomial time. Therefore, different heuristic processor allocation algorithms are proposed to reduce task worst-case response time (WCRT) [16]. However, existing works do not consider the topology of DAG tasks and the impact of self-interference, leading to pessimism or long response times for tasks in the analysis. For example, if figure 1 In Vi;2 and Vi;3 are allocated on processor 2, which will cause interference with each other; if they are allocated on different processors, they can run in parallel.

[0061] Aiming at this problem, the present invention proposes a new processor allocation strategy, which u...

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Abstract

The invention provides a division scheduling-based heuristic processor division method and system for a DAG task and a storage medium. The method comprises the steps of firstly deriving response timeanalysis of the DAG task based on a partition fixed priority scheduling algorithm; based on the intuition of analysis, the invention provides a processor allocation strategy of a greedy parallel execution cluster (GPEC), and the strategy considers the topological structure of a DAG task and the self-interference among sub-tasks in the task. The invention has the beneficial effect that the GPEC strategy of the invention considers the influence of the internal topological structure and self-interference of the DAG task. In addition, a real-time system is transplanted to the embedded board, and the performance of the GPEC strategy is evaluated on a real platform. Compared with two latest processor allocation strategies in an experiment, the GPEC strategy disclosed by the invention has the advantages that the average WCRT is reduced by 35.59% at most, and the schedulable rate of a DAG task set is increased by 76% at most.

Description

technical field [0001] The present invention relates to the technical field of data processing, in particular to a heuristic processor division method, system and storage medium for DAG tasks based on division scheduling. Background technique [0002] With the ever-increasing number of processors and the stringent requirement to complete massive calculations before deadlines, more and more applications are being migrated to embedded multiprocessor platforms of different types of mobile terminals and edge clouds [1], [2 ] are executed in parallel. These parallel programs can usually be represented by a directed acyclic graph (DAG) task model, where a DAG task consists of subtasks and edges connecting the subtasks [3]. Subtasks represent sequential computations, and edges represent dependencies between connected subtasks. [0003] figure 1 A real-time obstacle avoidance application for autonomous vehicles is shown. In this case, there is an obstacle in front of the vehicle...

Claims

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Application Information

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IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4881G06F9/5027
Inventor 张伟哲吴毓龙何慧方滨兴
Owner HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL