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A heuristic processor partition method, system and storage medium for dag tasks based on partition scheduling

A processor, heuristic technology, applied in the field of data processing, can solve problems such as unclear

Active Publication Date: 2021-10-15
HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL
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  • Application Information

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Problems solved by technology

However, under partition fixed priority scheduling, how to allocate subtasks of DAG tasks to reduce worst-case response time and improve task schedulability is still unclear

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  • A heuristic processor partition method, system and storage medium for dag tasks based on partition scheduling
  • A heuristic processor partition method, system and storage medium for dag tasks based on partition scheduling
  • A heuristic processor partition method, system and storage medium for dag tasks based on partition scheduling

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Embodiment Construction

[0060] The invention discloses a heuristic processor division method of DAG tasks based on division scheduling. The invention studies the processor allocation problem of fixed priority division scheduling of parallel DAG tasks on multi-processors. Since the problem has been shown to be NP-hard [15], one cannot hope to find an optimal processor allocation strategy in polynomial time. Therefore, different heuristic processor allocation algorithms are proposed to reduce task worst-case response time (WCRT) [16]. However, existing works do not consider the topology of DAG tasks and the impact of self-interference, leading to pessimism or long response times for tasks in the analysis. For example, if figure 1 In Vi; 2 and Vi; 3 are allocated on processor 2, which will cause interference between each other; if they are allocated on different processors, they can run in parallel.

[0061] Aiming at this problem, the present invention proposes a new processor allocation strategy, wh...

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Abstract

The present invention provides a heuristic processor division method, system and storage medium of a DAG task based on partition scheduling. The present invention first deduces a response time analysis of a DAG task based on a partition fixed priority scheduling algorithm; the intuition based on the analysis , the present invention proposes a greedy parallel execution cluster (GPEC) processor allocation strategy, which considers the topology structure of DAG tasks and the self-interference between subtasks within a task. The beneficial effects of the present invention are: the GPEC strategy of the present invention considers the internal topology structure of DAG tasks and the influence of self-interference. In addition, the present invention transplants the real-time system to the embedded board to evaluate the performance of the GPEC strategy on a real platform. Compared with the two latest processor allocation strategies in the experiment, the GPEC strategy of the present invention reduces the average WCRT by 35.59% at most, and the schedulability rate of the DAG task set increases by 76% at most.

Description

technical field [0001] The present invention relates to the technical field of data processing, in particular to a heuristic processor division method, system and storage medium for DAG tasks based on division scheduling. Background technique [0002] With the ever-increasing number of processors and the stringent requirement to complete massive calculations before deadlines, more and more applications are being migrated to embedded multiprocessor platforms of different types of mobile terminals and edge clouds [1], [2 ] are executed in parallel. These parallel programs can usually be represented by a directed acyclic graph (DAG) task model, where a DAG task consists of subtasks and edges connecting the subtasks [3]. Subtasks represent sequential computations, and edges represent dependencies between connected subtasks. [0003] figure 1 A real-time obstacle avoidance application for autonomous vehicles is shown. In this case, there is an obstacle in front of the vehicle...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4881G06F9/5027
Inventor 张伟哲吴毓龙何慧方滨兴
Owner HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL