Deep trench capacitor embedded in package substrate

Abstract

The invention relates to a deep trench capacitor embedded in a package substrate. In some aspects, a chip package includes an integrated circuit die having distribution circuitry for one or more circuits of an integrated circuit. The chip package also includes a substrate different from the integrated circuit, and the substrate has a first surface on which the integrated circuit die is mounted, and a second surface opposite to the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to a distribution circuit through a conductor.

Description

technical field [0001] The present disclosure relates to deep trench capacitors embedded in a packaging substrate. Background technique [0002] Dynamic noise (di / dt) in processor cores and application-specific integrated circuits (ASICs) is becoming increasingly problematic due to faster core clock frequencies and higher circuit current consumption. di / dt represents the rate of change of current to a load (eg, the core of an ASIC). Faster core clock frequencies cause more transient current to flow and thus more noise. In addition, higher di / dt noise results in higher voltage loss of power supplied to the circuit. Contents of the invention [0003] This specification describes techniques involving deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. [0004] In general, an innovative aspect of the subject matter described in this specification can be embodied in a chip package that includes an integrated circuit die including...

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