A kind of latch structure and latch method

A technology of buffer registers and flip-flops, which is applied in the field of latches, can solve the problems of signal loss, occupying a large chip area, and high power consumption, and achieve the effects of preventing information loss, small area overhead, and low power consumption.

Active Publication Date: 2022-04-22
浙江芯劢微电子股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the prior art, an analog latch must be used to latch an analog signal, resulting in large power consumption and occupying a large chip area; the digital frequency division latch, in the process of power failure, may cause glitches , making the latch fail;
[0004] On the other hand, the existing latch has no encryption function; and due to the high power consumption of the existing latch, after the main and auxiliary power supply is powered off, the latched signal is also lost

Method used

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  • A kind of latch structure and latch method
  • A kind of latch structure and latch method
  • A kind of latch structure and latch method

Examples

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Embodiment 1

[0052] Such as figure 1 As shown: a latch structure is disclosed, which realizes zero power consumption latch, occupies a very small chip area, increases the probability of latch failure after power failure, realizes encrypted latch and reset, and realizes power loss electrical latch.

[0053] It includes an analog-to-digital conversion circuit 100, including an analog signal receiving end 101 and a first digital signal output end 102;

[0054] The buffer register 200 includes a digital signal receiving end 201 and a second digital signal output end 202;

[0055] Encryption circuit 300, including at least one set of frequency circuits, control signal input terminals corresponding to the number of frequency division circuits, and an encrypted signal output terminal 301;

[0056] The first OR gate 400 includes a first clock signal input terminal 402, a first encrypted signal input terminal 401 and a first OR gate output terminal 403;

[0057] The second OR gate 500 includes a...

Embodiment 2

[0091] This embodiment discloses a latching method based on the latching circuit in Embodiment 1, and specifically relates to a latch that realizes zero power consumption, occupies a very small chip area, and increases the latch failure of the latch after power off. The probability of realizing encrypted locking and reset, and realizing power-down locking:

[0092] (1) Latching of analog signals

[0093] converting the analog signal into a first digital signal, and inputting the first digital signal to a first data input terminal of a first flip-flop;

[0094] Separately divide and process at least one group of control signals, and output encrypted signals after the frequency-divided control signals pass through AND gate logic;

[0095] inputting the encrypted signal as a clock signal of the first flip-flop to a clock terminal of the first flip-flop, and outputting latched data;

[0096] Specifically, the input analog signal S1 is converted by the analog-to-digital conversio...

Embodiment 3

[0113] In this embodiment, the difference from Embodiment 1 is that the encryption circuit uses a frequency division circuit, such as a frequency division circuit of 8 or a frequency division circuit of 10, and removes the three-input AND gate in Embodiment 1, and finally The Q terminal of the first-level D flip-flop outputs to the OR gate.

[0114] It should also be noted that in the structural naming of this technical solution, there is no functional specificity, such as "encryption circuit" and "encryption signal", which do not refer to the meaning of only encryption function. The actual technical characteristics of the "encryption circuit" According to this embodiment, the meaning of the example description shall prevail.

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Abstract

The present invention provides a latching structure and latching method, comprising an analog-to-digital conversion circuit, a buffer register, an encryption circuit, a first OR gate, a second OR gate, a first flip-flop and a second flip-flop. The output ends of the encryption circuit are respectively Connect the first OR gate and the second OR gate, the first OR gate is connected to the first flip-flop, the second OR gate is connected to the second flip-flop, the first flip-flop and the second flip-flop output the analog signal latch signal and the digital signal respectively Latch signal; wherein the analog-to-digital conversion circuit and the buffer register are connected to the first power supply; the encryption circuit, the first OR gate, the second OR gate, the first flip-flop and the second flip-flop are connected to the second power supply, and the second power supply is connected to a capacitor . Based on the above solution, a latch circuit capable of latching both analog signals and digital signals is realized, wherein the latch is constructed of all-digital gate logic, with small area overhead and low power consumption.

Description

technical field [0001] The invention relates to latch technology, in particular to the encrypted latch technology for realizing analog and digital signals. Background technique [0002] A latch is a pulse-level-sensitive memory cell circuit that changes state in response to a specific input pulse level. Latch is to temporarily store the signal to maintain a certain level state. The main function of the latch is to cache, secondly to complete the high-speed control and the out-of-sync problem with the slow peripherals, then to solve the problem of the driver, and finally to solve the problem that an I / O port can output and input question. [0003] In the prior art, an analog latch must be used to latch an analog signal, resulting in large power consumption and occupying a large chip area; the digital frequency division latch, in the process of power failure, may cause glitches , making the latch fail; [0004] On the other hand, the existing latch has no encryption functi...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G11C7/10
CPCG11C7/1087G11C7/106
Inventor张智印
Owner浙江芯劢微电子股份有限公司