Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element includes a device substrate including a device structure layer and a buried dielectric layer disposed on a semiconductor layer of the device structure layer. A metal layer is disposed on the buried dielectric layer and surrounded by a first inner dielectric layer. A region of the metal layer has a plurality of openings, wherein the buried dielectric layer has an air gap, the air gap is under the region of the metal layer having the plurality of openings and exposes the region. And a second inner dielectric layer disposed on the metal layer and sealing the air gaps by the plurality of openings of the metal layer.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing technology, and in particular to a structure of a semiconductor element and a manufacturing method thereof. Background technique [0002] In the development of semiconductor manufacturing technology, the manufacturing process can use a silicon-on-insulator (SOI) substrate to manufacture semiconductor elements. The silicon-on-insulator substrate has a thin semiconductor layer, such as a silicon layer, which can provide the semiconductor characteristics of the device, such as providing the channel effect of the field effect transistor. [0003] The semiconductor circuit can use a silicon substrate on an insulating layer to manufacture semiconductor elements, and in addition, an internal connection structure for connection and other required elements can be formed on both sides of the substrate. The interconnection structure is generally manufactured in conjunction with the inner dielectric l...

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Problems solved by technology

As is generally known, the increase of parasitic capacitance will increase the resistance-capacitance (RC) effect and reduce the operating speed

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