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Network processor system for supporting QoS based on FPGA and data package processing method

A network processor and data packet technology, applied in transmission systems, digital transmission systems, data exchange networks, etc., can solve the problems of inability to classify, inefficient classification algorithms, and inefficient queue management methods.

Inactive Publication Date: 2004-10-06
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] 1) The efficiency of the classification algorithm is not high, and each IP packet of the high-speed interface cannot be classified:
[0004] 2) Queue management is not efficient

Method used

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  • Network processor system for supporting QoS based on FPGA and data package processing method
  • Network processor system for supporting QoS based on FPGA and data package processing method
  • Network processor system for supporting QoS based on FPGA and data package processing method

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Embodiment Construction

[0041] The network processor architecture of the present invention is as figure 1 As shown, it is mainly composed of the following circuits and interfaces:

[0042] 1. Link layer processing circuit (1-1): This circuit processes the Ethernet frame to realize the second layer control protocol (wherein the address resolution protocol (ARP) table part is realized by the lookup circuit (1-3)). Since multiple Gigabit Ethernet interface controllers can be connected externally, this circuit also needs to realize data multiplexing and branching functions.

[0043] 2. Baotou processing circuit (1-2): carry out the processing of IP Baotou (carry out IP Baotou verification, check the life cycle of IP packet and subtract it by one), propose routing search and the request of IP packet classification simultaneously, according to result will The IP packet is sent to the CPU interface (1-8) or sent to the input queue circuit (1-4) for buffering.

[0044] 3. Search circuit (1-3): The search c...

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Abstract

The invention belongs to the IP technique area including the network processor system and the data packages processing method based on FPGA and supporting OoS. The system and method are realized by use of FPGA and includes following parts: the link layer process circuit interlinked with multiple Ethernet controllers; the package head process circuit, whose input end is connected to the link layer process circuit; the look up circuit interlinked with above two circuits; the input queue circuit, the dispatch circuit, the exchange network interface; the output queue circuit and the package sending circuit; the external of general CPU interface; multiple queue FIFO storage interface and the exchange network interface etc. The invention can process IP packages quickly and support IP QoS.

Description

technical field [0001] A field programmable gate array (FPGA)-based network processor system for supporting quality of service (QoS) and a data packet processing method belong to the technical field of IP quality of service. Background technique [0002] The network processor combines the advantages of an application-specific integrated circuit (ASIC) and a general-purpose CPU. It has the advantages of shortening the development cycle of the router and prolonging the life cycle of the router. It is an important component of the router. Many manufacturers have launched network processor products, and they all realize the basic functions of network processors, including: IP packet header processing, route lookup, IP packet cache, scheduling, etc. There are some network processors capable of caching and scheduling multiple queues and classifying IP packets, but their approach has the following disadvantages: [0003] 1) The efficiency of the classification algorithm is not hig...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/02H04L12/24H04L12/863
Inventor 刘斌李旭东戴智伟
Owner TSINGHUA UNIV