Clock pulse generating circuit

A technology for generating circuits and clock pulses, applied in time-division multiplexing selection devices, electrical components, generating/distributing signals, etc., can solve problems such as available frequency limitations, and achieve the effect of slowing down frequency limitations and avoiding abnormalities
CN1913720AInactive Publication Date: 2007-02-14RICOH KK
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
RICOH KK
Publication Date
2007-02-14
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The invention is to obtain a clock generation circuit having a PLL circuit and capable of evading the generation of abnormality at the switching of clocks independently of the signal levels of a current reference frequency dividing clock and a switched reference frequency dividing clock and the signal level of a comparing frequency dividing signal at the switching of clocks, and capable of sharply easing limitation in frequencies to be used for an input reference clock. Immediately after switching of input clocks CLK1, CLK2, first and second reference frequency dividing circuits 16, 17 and first and second comparing frequency dividing circuits 19, 20 are respectively reset, a pulse signal C is respectively added to a reference selection clock SEL1 outputted from a first selection circuit 15 and a comparison selection clock SEL2 outputted from a second selection circuit 18 and respective clocks SEL1, SEL2 to which the pulse signal C is respectively added are inputted to the PLL circuit 11.
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Description

technical field

[0001] The present invention relates to a clock pulse (Clock) generating circuit with a PLL (Phase Lock Loop) circuit, wherein switching selection is performed among complex input clock pulses, the selected clock pulse is used as a reference clock pulse, and based on the reference clock pulse A clock pulse of a predetermined frequency is generated and output. Background technique

[0002] Figure 4 It is a block diagram illustrating an example of the prior art (for example, JP-A-7-170584). Figure 5 is attached Figure 4 The timing diagram of the waveform of each signal.

[0003] exist Figure 4 In the clock pulse generation circuit 100 shown, the first input reference clock pulse 101, the second input reference clock pulse 102 and the third input reference clock pulse 103 are respectively input into the corresponding frequency division circuits 121-123, and passed through each frequency division Circuits 121-123 are converted into reference frequency-divid...

Claims

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