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Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels

一种微通孔、连接到的技术，应用在电气连接印刷元件、半导体/固态器件零部件、印刷电路等方向，能够解决器件功能性起负面影响、不合乎要求等问题

Inactive Publication Date: 2011-05-11
ALCATEL LUCENT SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] Prior art solutions have additional restrictions on the pinout configuration (pinout) of the power and ground of the area array device, that is, a special pinout mode must be strictly adhered to, which in extreme cases is passed through a certain pinout configuration. Area array package style may not be possible
Generally, these additional constraints are undesirable from a signal integrity point of view
In addition, this solution involves sharing adjacent power and ground pins, which is also an unfavorable implementation that can negatively impact the functionality of the device

Method used

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  • Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels
  • Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels
  • Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels

Examples

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Embodiment Construction

[0022] Figure 1 is a top view of a printed circuit board (PCB) surface incorporating a prior art solution. Ball grid array (BGA) ball contact pads 10 are connected to through-board vias 12 through links 11 . To provide routing channels 20, selected rows of ball contact pads 15 and 16 are connected by links 17 and 18 to a common through-board via 19, which is designated here as a shared through-board via. The disadvantages of this solution are described above.

[0023] The invention is Figure 2a , 2b and 2c to illustrate. (Original labeled components correspond to those in Figure 1.) The first three-layer circuit board is shown to illustrate the BGA package specification.

[0024] By creating columns and / or rows of microvias interspersed in columns / rows of regular vias every other row, the columns and rows of vias at these locations can be eliminated. exist Figure 2a , the columns MVC1, MVC2, MVC3... of micro vias are scattered in each column of regular vias C1, C2, C3......

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Abstract

A printed circuit board having micro-vias used to connect a portion of the contacts in a selected row or column to the first internal layer of the board, thereby creating routing channels on the second and subsequent internal layers of the board between selected rows or columns of through-board vias used to connect the remaining contacts and a BGA package adapted to be used with the printed circuit board.

Description

[0001] Cross References to Related Applications [0002] This application is related to the following U.S. patent applications assigned to the present assignee: [0003] Application No. 10 / 991,360, filed November 19, 2004, inventor Paul Brown, title OFF-WIDTH PITCH FOR IMPROVED CIRCUIT CARDROUTING; and [0004] Application No. 11 / 041,727, submitted on January 25, 2005, inventor Alex Chan, invention name OFF-GRID DECOUPLING OF BALL GRID ARRAY (BGA) DEVICES. technical field [0005] The present invention relates to improving the efficiency of signal extraction from area array packages (BGA and CGA) and routing of signals on a printed circuit board (PCB or circuit board) on which circuit components are mounted. Background technique [0006] It is well established that an increase in area array connections (total pin count) translates to an increase in the number of printed circuit board wiring layers and routing circuits required to support device escapes. The motivation to f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H05K1/16H05K1/11H01L23/00
CPCH01L23/49816H01L23/49827H01L23/49838H01L23/50H05K1/114H05K3/429H05K2201/09227H05K2201/09509H05K2201/10734H01L2924/0002H01L2924/00
Inventor P·J·布朗
Owner ALCATEL LUCENT SAS
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