Method of and apparatus for controlling probe tip sanding in semiconductor device testing equipment

Abstract

In a method of and apparatus for controlling probe tip sanding in semiconductor device testing equipment, resistance values of pads of a probed chip are measured and stored. If a maximum resistance value among the stored resistance values is greater than a contact resistance reference value, a consecutive fail counting value and an accumulated fail counting value are increased. An automatic sanding command is generated to activate automatic sanding of a probe tip, when at least one of the consecutive fail counting value and the accumulated fail counting value is greater than a respective counting reference value. In this manner, false negative readings in the testing of semiconductor devices as the result of increased contact resistance between a probe tip and a pad in an EDS test are reduced and therefore device yield is improved.

Description

RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10 / 649,250, filed on Aug. 26, 2003, which relies for priority upon Korean Patent Application No. 2002-0056333, filed on Sep. 17, 2002, the contents of which are herein incorporated by reference in their entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to test equipment for a semiconductor device; and more particularly, to a probe tip sanding control method and apparatus. [0004] 2. Description of the Related Art [0005] An electrical die sorting (EDS) test for the testing of semiconductor devices is well-known in the art, and is performed at the wafer level, as opposed to the package level. At the wafer level, the semiconductor device has not yet been placed in a package, and therefore does not include leads. Thus, the EDS test employs a probe card having probe tips that access device circuitry. When a probe card tip is in contact with a p...

AI Technical Summary

Benefits of technology

[0009] An object of the present invention is to provide a method of controlling probe tip sanding in semiconductor device test equipment, which is capable of mitigating or eliminating the limitations associated with the conventional approaches.

[0011] Another object of the present invention is to provide a method and apparatus for controlling probe tip sanding in semiconductor device test equipment, in order to minimize false negative readings related to the proper operation of semiconductor devices under test caused by the augmentation of contact resistance between a probe tip and a pad in an EDS test.

[0012] An additional object of the present invention is to provide a method and apparatus for controlling probe tip sanding for semiconductor device testing equipment, in order to reduce the overall testing time and in order to optimize the useful life of the probe tip by performing probe tip sanding periodically over an optimized period.

Problems solved by technology

This augmented contact resistance disturbs normal contact in an open / short (O / S) test as one of basic DC measurements, affects the linearity of an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) utilized in an analog block test, and affects certain measuring procedures, such as a gain error etc.

This, in turn, can lead to erroneous readings as to whether a device under test meets the criteria for proper operation.

Therefore, a normal semiconductor device can be dismissed as a bad part as a result of the test procedure, which, in turn, can have an adverse effect on yield, and therefore leads to a rise in manufacturing costs.

Such a yield reduction caused by an augment of the tip contact resistance drops can therefore affect even the operating rate of the equipment.

In the meantime, frequent sanding of the probe tip slows down the test procedure, owing to increased time required for tip sanding, and, in addition, the useful life span of the probe tip is shortened.

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