Adaptive thread id cache mechanism for autonomic performance tuning

a cache mechanism and thread id technology, applied in the field of computer architecture, can solve the problems of increasing cache misses, substantial affecting the performance of the computer system, and increasing cache misses for the second application, so as to inhibit data cache thrashing, and increase the level of associativity in the data cach

Inactive Publication Date: 2008-01-10
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively reduces cache thrashing and minimizes additional delays in data access by dividing the cache into thread-specific regions, ensuring that data needed by one application is not discarded due to misses from another, thereby enhancing system performance in multi-threading modes.

Problems solved by technology

Memory access is essential in any computer system and substantially affects the performance of a computer system.
Cache misses increase especially when a computer is executing in a simultaneous multi-threading mode.
In a multi-threading mode, multiple applications access the memory simultaneously and a cache miss by one application may thrash the cache for a second application by removing a data needed by the second application and thus causing a cache miss for the second application.
After the two pieces of data is retrieved from the cache memory, additional steps must be taken to select one of them for the application's use, thus adding more delay to the data access.
This additional delay becomes especially aggravated when the number of data simultaneously retrieved increases.

Method used

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  • Adaptive thread id cache mechanism for autonomic performance tuning
  • Adaptive thread id cache mechanism for autonomic performance tuning
  • Adaptive thread id cache mechanism for autonomic performance tuning

Examples

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Embodiment Construction

[0015] In this description, like numerals refer to like elements throughout the several views. The invention temporarily divides a cache to inhibit thrashing and to simulate the performance of higher level associativity. The cache is divided using thread ID bits without requiring extra select time.

[0016] Generally, a one level (L1) cache is unable to implement a high set associativity to support a simultaneous multi-threading execution mode without significant costs in area, power, additional access latency, and significant redesign resource and schedule. FIG. 1A illustrates a problem with a L1 cache. An address generator 105 generates an effective address 106 using information from two registers RA 102 and RB 104. The effective address 106 is fed to a cache memory 107 having two sets of data 108 and 110. The effective address is connected to two comparators 114 and 116 for use in a 2-way late selecting unit 118, which will select which data to output to a cache data bus.

[0017] Th...

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Abstract

An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register. The data cache is split when the apparatus is in the multi-threading execution mode indicated by an enable cache split bit.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] This application is a continuation of, and claims the benefit of, U.S. patent application Ser. No. 10 / 670,717, filed Sep. 25, 2003, the entirety of which is hereby incorporated herein by reference. In the parent case, Ser. No. 10 / 670,717, claims 1-2, 4-6 and 10 were rejected under 325 USC 102(b) as anticipated by US Patent Application Publication No. 2006 / 0195683 A1 filed by Kissell. Applicant disagrees on the grounds that the present invention was invented prior to the invention of the Kissell reference, as evidenced by the Affidavit pursuant to 37 C.F.R., section 1.131, filed with respect to U.S. patent application Ser. No. 10 / 670,717. For this reason, applicant believes he is entitled to the broader claims now presented. Applicant rescinds any disclaimer in the parent application that may have resulted from the amendment to the claims of the parent application that lead to the allowance of the claims therein and requests that the e...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F12/00G06F9/38G06F12/08
CPCG06F9/3824G06F12/0848G06F12/0842G06F9/3851
InventorLUICK, DAVID A.
OwnerINT BUSINESS MASCH CORP