High Speed And Low Power Sense Amplifier

Inactive Publication Date: 2016-09-01
SILICON STORAGE TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a method for accessing data stored in a computer chip using a sense circuit that compares the stored bits with bits generated by accessing the same bit line in another bank. This method eliminates the need for separate reference cell circuits. The technical effect is to improve the efficiency and accuracy of accessing data in a computer chip.

Problems solved by technology

This prior art system can be adversely affected by changes in the parasitic capacitance of the system.
Another challenge in the prior art is that memory systems can provide incorrect values if there is significant leakage current caused by defects in one or more transistors.

Method used

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  • High Speed And Low Power Sense Amplifier
  • High Speed And Low Power Sense Amplifier
  • High Speed And Low Power Sense Amplifier

Examples

Experimental program
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Embodiment Construction

[0016]An embodiment will now be described with reference to FIG. 1. Memory system 100 comprises array 30 and array 40, which typically are identical memory arrays of floating gate memory cells. Address lines 80 carry the address signals of the memory location to which the read or write operation applies. Address decoder 10 and address decoder 20 decode the address carried on address lines 80 and activate the appropriate word line and bit line in array 30 or array 40 so that a word of data is read from the correct location or a word of data is written to the correct location. As part of this operation, address decoder 10 controls bit line multiplexer 50, and address decoder 20 controls bit line multiplexer 60.

[0017]As an example, during a read operation of a particular address in array 30, the appropriate word line X and bit line Y will be activated in array 30, and bit line multiplexer 50 will output word 95 from that location in array 30 as an input to comparator 70. Concurrently, ...

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Abstract

An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

Description

TECHNICAL FIELD[0001]An improved sense amplifier for reading a non-volatile memory cell is disclosed.BACKGROUND OF THE INVENTION[0002]Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.[0003]Read operations usually are performed on floating gate memory cells using sense amplifiers. A sense amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “'158 Patent”), which is incorporated herein by reference for all purposes. The '158 Patent discloses using a reference cell that draws a known amount of current. The '158 Patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current mirror to mirror the current drawn by the selected memory cell. The current in each current mirror is then...

Claims

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Application Information

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IPC IPC(8): G11C16/28G11C16/24G11C16/08
CPCG11C16/28G11C16/24G11C16/08G11C7/062G11C7/12G11C7/14G11C29/025G11C2029/1204G11C2029/5006
InventorPI, XIAO YANQIAN, XIAOZHOUYUE, KAI MANZHOU, YAOZHU, YAOHUA
OwnerSILICON STORAGE TECHNOLOGY