Output stage circuit for transmitting data via bus

a technology of output stage and data, applied in the direction of diodes, electronic switching, pulse techniques, etc., can solve the problems of data transmission error and high cost of soi manufacturing process, and achieve the effect of reducing the coupling

Active Publication Date: 2021-04-22
RICHTEK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes the circuitry used in high side and low side clamps. Each circuit includes a Zener diode, a resistor, and a capacitor to reduce coupling effects caused by parasitic capacitance. The high side clamp ensures the MOSFET is turned on and limits the current flow through the Zener diode, while the low side clamp ensures the MOSFET is turned on and limits the current flow through the Zener diode and reduces the coupling effect caused by the drain parasitic capacitance. The circuitry also includes a boost converter to generate a second voltage level higher than the first voltage level. The technical effects of this patent text are to improve the stability and efficiency of power conversion circuits by reducing coupling effects and improving the performance of clamp circuits.

Problems solved by technology

Consequently and undesirably, operation error of the high side switch QH1 or the low side switch QL1 will occur, resulting in data transmission error.
Although the SOI manufacturing process can avoid forming the parasitic BJT, the SOI manufacturing process is costly, as compared to the standard CMOS manufacturing process.

Method used

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  • Output stage circuit for transmitting data via bus
  • Output stage circuit for transmitting data via bus
  • Output stage circuit for transmitting data via bus

Examples

Experimental program
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Effect test

first embodiment

[0038]Please refer to FIGS. 2A-2C, which show the present invention. FIG. 2A shows a schematic diagram of an output stage circuit 21 configured to operably transmit data via a bus. As shown in FIG. 2A, the output stage circuit 21 comprises a controller 211 and a transceiver circuit 213. The controller 211 controls the transceiver circuit 213, to transmit or receive data via the bus (referring to the above-mentioned bus 12). The bus has a high side signal line, a low side signal line and an impedance circuit coupled between the high side signal line and the low side signal line. For example, as shown in FIG. 1A, the impedance circuit can include, for example but not limited to, two resistors RL. Each resistor RL has its two ends electrically connected to the high side signal line and the low side signal line, respectively. The high side signal line has plural high side output terminals CANH, which are respectively coupled to the corresponding data transceiver controller circuits 21. ...

second embodiment

[0050]Please refer to FIGS. 3A-3G, which show the present invention. FIG. 3A shows a schematic diagram of an output stage circuit 31 configured to operably transmit data via a bus. As shown in FIG. 3A, the output stage circuit 31 comprises a controller 311 and a transceiver circuit 313. The controller 311 can control the transceiver circuit 313, such that the output stage circuit 31 can transmit or receive data via the bus (referring to the above-mentioned bus 12). The bus has a high side signal line, a low side signal line and an impedance circuit coupled between the high side signal line and the low side signal line. For example, as shown in FIG. 1A, the impedance circuit can include, for example but not limited to, two resistors RL. Each resistor RL has its two ends electrically connected to the high side signal line and the low side signal line, respectively. The high side signal line has plural high side output terminals CANH, which are respectively coupled to the corresponding...

third embodiment

[0066]Please refer to FIG. 4, which shows the present invention. FIG. 4 shows a schematic diagram of an output stage circuit 41 configured to operably transmit data via a bus. As shown in FIG. 4, the output stage circuit 41 comprises a controller 411 and a transceiver circuit 413. The controller 411 can control the transceiver circuit 413, such that the output stage circuit 41 can transmit or receive data via the bus (referring to the above-mentioned bus 12). On one hand, each data transceiver controller circuit 41 can generate a differential output signal between the corresponding high side output terminal CANH and the corresponding low side output terminal CANL, so as to transmit data. On the other hand, each data transceiver controller circuit 41 can receive a differential input signal via the corresponding high side output terminal CANH and the corresponding low side output terminal CANL, so as to receive data.

[0067]Please still refer to FIG. 4. In the data transceiver controlle...

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Abstract

An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.

Description

CROSS REFERENCE[0001]The present invention claims priority to TW 108137277 filed on Oct. 16, 2019.BACKGROUND OF THE INVENTIONField of Invention[0002]The present invention relates to an output stage circuit configured to operably transmit data via a bus; particularly, it relates to such output stage circuit capable of withstanding positive and negative voltages.Description of Related Art[0003]Please refer to FIG. 1A, which shows a schematic diagram of a conventional controller area network (CAN) 1. The CAN 1 comprises plural data transceiver controller circuits 11 and a bus 12. Each data transceiver controller circuit 11 includes a controller 111 and a transceiver circuit 113. The controller 111 can control the transceiver circuit 113 to transmit or receive data via the bus 12. The bus 12 has a high side signal line, a low side signal line and an impedance circuit coupled between the high side signal line and the low side signal line. As shown in FIG. 1A, the impedance circuit can in...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H03K17/16H01L27/02
CPCH03K17/161H01L27/0266H01L27/0255H03K2217/0072H01L27/0285H03K2217/0063H01L27/0259H03K17/16H03K17/162H03K17/602
InventorCHANG, YU-WENHSIU, LENG-NIENCHEN, ISAAC Y.
OwnerRICHTEK TECH