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Embedded packaging structure and its packaging method

A technology of packaging structure and packaging method, which is applied in the direction of electrical components, electric solid devices, circuits, etc., and can solve problems such as application restrictions

Active Publication Date: 2008-02-27
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] To sum up, the two embedded packaging structures have their disadvantages, which limit their application

Method used

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  • Embedded packaging structure and its packaging method
  • Embedded packaging structure and its packaging method
  • Embedded packaging structure and its packaging method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0037] Please refer to FIGS. 3A to 8, which are schematic diagrams of a preferred embodiment of the packaging process of the embedded packaging structure of the present invention. First, referring to FIG. 3A, a wafer W is provided, and a plurality of semiconductor elements (not shown) and a plurality of metal pads 410a are fabricated on the wafer W. These semiconductor elements exchange electronic signals with the outside through the metal pad 410a.

[0038] Subsequently, as shown in FIG. 3B, an insulating layer 420 (passivation layer) is formed on the upper surface of the wafer W to cover the metal pad 410a. Please also refer to FIG. 4, which is a partial top view of the wafer W. As shown in the figure, the insulating layer 420 does not cover all the metal pads 410a, 410b on the surface of the chip 400, but only covers them to enable the semiconductor components on the chip 400 to exchange electronic signals with the outside world, that is, as the output of the chip 400 The metal...

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PUM

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Abstract

The invention relates to an embedded package with a sealed base plate, a sealing chip, an insulating layer and a wire arranging layer. The upper surface of the chip has at least one mental pad. The chip embedded into the sealed base plate with exposing upper surface. The insulating layer is covered on the chip with at least on hole to expose on the upper surface of the mental pad. The wire arranging layer is on the upper of the insulating layer. The bottom of the wire arranging layer has a tuck into the hole and connected with the mental pad. The top of the wire arranging layer has a touching pad. It also provides a chip sealed method.

Description

Technical field [0001] The invention relates to an embedded packaging structure and a packaging method thereof, in particular to an embedded packaging structure using built-up layer technology and a packaging method thereof. Background technique [0002] With the development of semiconductor technology, the demand for thinner and lighter packaging structures has gradually increased. Based on this, the embedded packaging technology has begun to attract attention. The embedded packaging structure makes a hole in a packaging substrate, and embeds the chip to be packaged in the hole, thereby reducing the thickness of the entire packaging structure to meet the requirements of lightness and thinness. [0003] Please refer to FIGS. 1A to 1E, which are schematic diagrams of the packaging process of a typical embedded packaging structure. Regarding a chip 200 to be packaged, as shown in FIG. 1A, a semiconductor element (not shown) fabricated on the chip 200 exchanges electronic signals wi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L21/60
CPCH01L2924/01015H01L2924/18162H01L2924/01033H01L2924/01005H01L2924/15311H01L2924/01006H01L2924/01029H01L24/19H01L2224/20H01L2924/01074H01L2924/01013H01L2224/04105H01L2224/19H01L2924/00012
Inventor 张文远杨智安
Owner VIA TECH INC