Embedded packaging structure and its packaging method
A technology of packaging structure and packaging method, which is applied in the direction of electrical components, electric solid devices, circuits, etc., and can solve problems such as application restrictions
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[0037] Please refer to FIGS. 3A to 8, which are schematic diagrams of a preferred embodiment of the packaging process of the embedded packaging structure of the present invention. First, referring to FIG. 3A, a wafer W is provided, and a plurality of semiconductor elements (not shown) and a plurality of metal pads 410a are fabricated on the wafer W. These semiconductor elements exchange electronic signals with the outside through the metal pad 410a.
[0038] Subsequently, as shown in FIG. 3B, an insulating layer 420 (passivation layer) is formed on the upper surface of the wafer W to cover the metal pad 410a. Please also refer to FIG. 4, which is a partial top view of the wafer W. As shown in the figure, the insulating layer 420 does not cover all the metal pads 410a, 410b on the surface of the chip 400, but only covers them to enable the semiconductor components on the chip 400 to exchange electronic signals with the outside world, that is, as the output of the chip 400 The metal...
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