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Data processing apparatus and data processing system

A technology for a data processing device and a data processing system, which is applied in electrical digital data processing, memory systems, televisions, etc., can solve problems such as delay and delayed transmission, and achieve the effect of preventing the reduction of total processing capacity

Inactive Publication Date: 2009-06-03
RENESAS ELECTRONICS CORP
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

Figure 4 A situation is shown in which the end of the i-th unit process in the data processing engine 100 is delayed for some reason, so the transmission of the i+1-th unit process start signal 101 is delayed

Method used

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  • Data processing apparatus and data processing system
  • Data processing apparatus and data processing system
  • Data processing apparatus and data processing system

Examples

Experimental program
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Embodiment Construction

[0049] 1. Outline of Embodiment

[0050] First, an outline of a typical embodiment of the invention disclosed in this application will be described. The reference symbols in the drawings that are referred to in parentheses in the summary description of the representative embodiments are merely examples of components included in the concept of the constituent elements to which the symbols are added.

[0051] [1] The data processing device (50) includes: a data processing unit (100), which uses the data sequentially read from the storage device to perform data processing; The device outputs a burst transfer request (301); and a timing generation unit (503) generates a burst transfer request to the above-mentioned burst transfer request based on a request signal (101) output from the above-mentioned data processing unit according to each processing unit of its data processing. section provides output timing for burst transfer requests. When the elapsed time from the output of t...

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Abstract

Decrease in throughput performance called a 'jamming' in a memory device is prevented. There is provided a timing generation part which gives, based on a request signal outputted for each unit of the data processing from a data processing part, an output timing for a burst transfer request to a burst transfer request generation part. Based on the relationship in size between a lapsed time from the output of the burst transfer request to the activation of the request signal and a time specified by a set threshold value of a threshold value register, the timing generation part controls output timing for a burst transfer request. When the lapsed time exceeds the time specified by a maximum threshold value, the burst transfer request generation part is given an output timing for the burst transfer request without waiting for the activation of the request signal. As a result, when the issuance of the request signal is delayed, a next burst transfer request can be given to the memory device without waiting for the issuance but preceding it.

Description

technical field [0001] The present invention relates to the control of a storage device based on burst transfer, and relates to a semiconductor device such as a SOC (system on chip: system on a chip) having a CODEC (system on chip: system on chip) that performs encoding and decoding processing of image data in units of display frames, and data Technology for processing systems. Background technique [0002] In order to improve the performance of a data processing device, or a data processing engine such as a processor or an accelerator disposed in the data processing device, it is particularly important to realize efficient memory access control. [0003] For example, when it is desired to perform image coding and decoding (codec) processing using a data processing engine, it is necessary to maintain a certain amount of data flow (total processing capacity) and simultaneously transfer a large amount of data to the data processing engine (burst transfer) data. Usually, in i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28H04N7/26G06F12/00
CPCG06F13/28
Inventor 本间一树见学彻
Owner RENESAS ELECTRONICS CORP
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