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Configurable cache for a microprocessor

A high-speed cache and high-speed cache technology, which is applied in the direction of memory systems, electrical digital data processing, instruments, etc., can solve the problems of limited and incapable of supporting high processing capacity and narrow memory

Active Publication Date: 2013-10-16
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Small microcontroller designs are limited by the amount of cache memory that can be located on-chip, and they cannot support large sizes of high-latency but high-throughput narrow memories

Method used

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  • Configurable cache for a microprocessor
  • Configurable cache for a microprocessor
  • Configurable cache for a microprocessor

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Embodiment Construction

[0023] A standard microcontroller unit (MCU) typically contains an 8-bit or 16-bit microprocessor core. 32-bit cores have only recently entered the MCU world. All of these cores typically have no cache memory. Only complex high-end 32-bit microcontrollers can have cache memory. This is because cache memory is large and expensive for an MCU. The disclosed embodiments provide a middle ground small configurable cache that can be configured on the fly and can act as a prefetch and branch trace buffer while providing optimal cache depth for MCU applications.

[0024] According to an embodiment, the cache memory may be designed to be configurable to operate very flexibly. For example, it can be programmed to operate strictly as a cache, which is useful for small loop optimizations. To do this, the corresponding cache line containing the loop can be manually locked. It can also contribute a certain number of cache lines (eg, up to half of the lines used to link branch history st...

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Abstract

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

Description

[0001] Cross References to Related Applications [0002] The title of this application claimed on December 15, 2006 is "CONFIGURABLE PICOCACHE WITHHPREFETCH AND LINKED BRANCH TRAIL BUFFERS, AND FLASH PREFETCHBUFFER)" and U.S. Provisional Application No. 60 / 870,622, filed December 19, 2006, entitled "LINKED BRANCH HISTORY BUFFER" ; both provisional applications are incorporated herein in their entirety. technical field [0003] The present invention relates to a configurable cache memory for a microprocessor or microcontroller. Background technique [0004] The bottleneck of the pipelined microprocessor architecture is the high access time of the memory system. Typical approaches to address this problem use large cache memories and transfer multiple data words per clock after an initial high memory access time. Small microcontroller designs are limited by the amount of cache memory that can be located on-chip, and they cannot support large sizes of high-latency but high-t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F12/0875G06F12/0895
Inventor 罗德尼·J·佩萨文托格雷格·D·拉赫蒂约瑟夫·W·特里斯
Owner MICROCHIP TECH INC