Semiconductor device and manufacturing method thereof
A technology of semiconductors and wires, which is applied in the field of semiconductor devices and its manufacturing, and can solve problems such as reduced connection life and weak bonding strength between pads and solder balls
Active Publication Date: 2014-08-06
RENESAS ELECTRONICS CORP
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
However, in SMD, since the bonding strength between the land and the solder ball is weakened, it is unavoidable to reduce the connection life when the BGA is mounted on the motherboard.
Method used
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[0178] In the following embodiments, for the sake of convenience, when necessary, they will be divided into multiple parts or embodiments for description. However, unless otherwise specified, these parts or embodiments are not unrelated to each other. Relationships such as modification examples, detailed descriptions, supplementary explanations, etc. of a part or the whole of one party.
[0179] In addition, in the following embodiments, when referring to the number of elements, etc. (including number, numerical value, amount, range, etc.), except for the case where it is specifically stated and the case where it is clearly limited to a specific number in principle, etc., it does not mean It is limited to a specific number, and may be greater than or equal to the specific number, or may be less than the specific number.
[0180] Furthermore, the constituent elements (including elemental steps, etc.) in the following embodiments are, of course, non-essential constituents, excep...
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Abstract
The present invention provides a technology capable of suppressing uneven height of solder balls when NSMD is used as a pad structure. A via hole V penetrating the wiring substrate 1S is provided. Further, a land LND3 is formed so as to be directly connected to the via hole V on the back surface of the wiring substrate 1S. This land LND3 is formed so as to be included in the opening K formed on the solder resist SR. Furthermore, the hemisphere HBa is mounted on the land LND3. That is, the present invention is characterized in that the connection structure between the land LND3 formed on the back surface of the wiring substrate 1S and the via V is a via-in-pad structure, and the configuration of the land LND3 is NSMD.
Description
technical field [0001] The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a wiring substrate on which a semiconductor chip is mounted and on a surface (back surface) opposite to the semiconductor chip mounting surface (surface) of the wiring substrate. A semiconductor device provided with terminals for external connection and an effective technique suitable for the manufacture of the semiconductor device. Background technique [0002] In Japanese Patent Application Laid-Open No. 2006-190928 (Patent Document 1), there is described a technology related to a BGA (Ball Grid Array, Ball Grid Array) that prevents the BGA from being formed on a wiring substrate. Voids or pits are formed in the through holes. In this technique, a via hole (blind via) that does not penetrate the wiring substrate is formed inside the wiring substrate, and a pad is formed on the back surface of the wiring substrate so as to be directly co...
Claims
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IPC IPC(8): H01L23/48H01L23/49H01L23/13H01L21/50H01L21/60
CPCH01L2924/01002H01L2224/73265H01L24/45H01L23/66H01L2924/01015H01L2224/48091H01L23/49816H01L2924/01004H01L2924/01078H01L2221/68331H01L24/48H01L2924/14H01L2924/01005H01L2924/01013H01L2924/01056H01L2224/45144H01L2924/30107H01L24/49H01L23/49838H01L2924/30105H01L2924/1306H01L2924/01051H01L24/83H01L24/85H01L2224/32225H01L2924/1305H01L24/97H01L2224/97H01L2924/01046H01L2924/01006H01L21/6835H01L2924/19041H01L2924/3011H01L2924/01028H01L2924/01079H01L2924/01074H01L2924/15311H01L2924/01038H01L2924/01014H01L2224/83192H01L2924/01082H01L2224/85H01L2224/49171Y10T29/49014H01L2924/014H01L2924/01023H01L2924/01029H01L2924/19043H01L2224/78301H01L2924/01019H01L2224/48227H01L2924/01033H01L23/49827H01L2924/181H01L2224/85181H01L2224/92247H01L24/73H01L2224/05553H01L2924/10162H01L2924/00014H01L2924/00H01L2924/00012
Inventor 团野忠敏
Owner RENESAS ELECTRONICS CORP