Testing apparatus, testing method, and program

Abstract

A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.

Description

technical field

[0001] The present invention relates to a test device, a test method, and a program for testing a circuit subject to inspection using test vector data in which an input signal to be input to the circuit subject to inspection is described. Background technique

[0002] In recent years, systems using electronic circuits have evolved to have higher functionality and more complexity. As a result, the hardware installed in such systems has a larger circuit size and increased complexity. In system design, verification of hardware and software is very important to ensure that the system performs as specified.

[0003] In hardware design, functional verification occupies most of the design time. As the size and complexity of circuits increases, so does the number of person-hours for verification of such functionality. Against this background, measures for shortening the verification of the function are considered. Exemplary methods of shortening the verification ...

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