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Testing apparatus, testing method, and program

一种测试装置、测试矢量的技术,应用在静态存储器、仪器等方向,能够解决大电路规模、增加复杂性等问题

Inactive Publication Date: 2010-10-06
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the hardware installed in such systems has a larger circuit size and increased complexity

Method used

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  • Testing apparatus, testing method, and program
  • Testing apparatus, testing method, and program
  • Testing apparatus, testing method, and program

Examples

Experimental program
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Embodiment Construction

[0034] A description of the embodiments of the present invention will be given in the following order with reference to the accompanying drawings:

[0035] 1. Embodiment (For each input signal used for verification, an example of generating test vector data by converting original test vectors with a probability of failure occurrence)

[0036] 2. Another embodiment (an example in which the failure occurrence probability of an input signal is changed corresponding to the failure occurrence of another input signal)

[0037]

[0038] [Configuration of test device]

[0039] A test device emulation circuit description program according to an embodiment of the present invention, in which a circuit (DUT: Design Under Test) subjected to inspection is described to check the function of the circuit. The test device can convert the test vector data created by the user in the simulation of the circuit description program with the failure occurrence probability of the signal to perform the...

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Abstract

A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.

Description

technical field [0001] The present invention relates to a test device, a test method, and a program for testing a circuit subject to inspection using test vector data in which an input signal to be input to the circuit subject to inspection is described. Background technique [0002] In recent years, systems using electronic circuits have evolved to have higher functionality and more complexity. As a result, the hardware installed in such systems has a larger circuit size and increased complexity. In system design, verification of hardware and software is very important to ensure that the system performs as specified. [0003] In hardware design, functional verification occupies most of the design time. As the size and complexity of circuits increases, so does the number of person-hours for verification of such functionality. Against this background, measures for shortening the verification of the function are considered. Exemplary methods of shortening the verification ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/08G11C29/10
CPCG11C29/10G11C29/56G11C29/56004
Inventor 近田慎一郎
Owner SONY CORP