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Processor supporting a plurality of command systems

A processor and instruction technology, applied in the field of processors supporting protocol instruction system, configuration instruction system and conventional instruction system, can solve the problems of low efficiency and inconvenience of system resources

Active Publication Date: 2014-01-29
北京多思技术服务有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when using security protocols frequently or in large quantities for security protocol communications (for example, in router applications), it is inconvenient to use software systems for security protocol communications, which may occupy a large amount of system resources but is inefficient

Method used

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  • Processor supporting a plurality of command systems
  • Processor supporting a plurality of command systems
  • Processor supporting a plurality of command systems

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Embodiment Construction

[0024] Those skilled in the art will understand that the following specific descriptions are only exemplary, and are intended to more clearly illustrate the general concept, idea, and structure of the present invention, rather than limiting the claims.

[0025] The processor of the present invention is a secure processor, which can be implemented as a secure coprocessor (secure chip), or a combination of a secure coprocessor and an MCU (MCPU), or a general processor with a secure processing core.

[0026] The processor of the present invention can support a protocol instruction system, and the protocol instruction system includes multiple instructions related to the security protocol, so as to realize various functions of the security protocol, such as identity authentication, encryption and decryption, and the like. In addition to supporting the protocol instruction system, the processor of the present invention can also support instructions of other instruction systems.

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PUM

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Abstract

The invention relates to a processor which is characterized in that at least part of the processor can be restructured. The processor comprises a first command system decoder and a second command system decoder, wherein the first command system decoder is used for decoding commands of a first command system which comprises a plurality of commands related to a safety protocol; and the second command system decoder is used for decoding commands of a second command system which comprises a plurality of commands related to a configuration file. The processor also comprises a third command system decoder used for decoding commands of a third command system which is different from the first command system and the second command system.

Description

technical field [0001] The present invention relates to a processor, specifically, to a processor supporting multiple instruction systems, and more specifically, to a processor supporting a protocol instruction system, a configuration instruction system and a conventional instruction system. Background technique [0002] With the rapid development of information technology, reconfigurable design has received more and more attention in the field of processors. [0003] Typically, reconfigurable logic consists of three parts: reconfigurable elements, controllable nodes, and the connection network between them. Recombination elements are used to realize the basic operation components of various algorithms, and are the basic elements used by reconfigurable logic to construct various algorithms. The network of connections between reorganized elements is used to establish the required data transmission pathways for the various algorithms. Obviously, the recombined elements and t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/76G06F9/30
Inventor 刘大力曹春春
Owner 北京多思技术服务有限公司