Single plate and method for upgrading same on line

Abstract

The invention provides a single plate. The single plate comprises a main control unit, a field programmable gate array (FPGA) unit, a first storage unit and a second storage unit, wherein the main control unit is used for loading minimum control logic from the FPGA unit, and reading a formal version of the FPGA from the second storage unit and storing the formal version after the minimum control logic is successfully loaded, and reloading the FPGA unit; the FPGA unit is used for automatically loading the minimum control logic from the first storage unit; the first storage unit is used for storing the minimum control logic; and the second storage unit is used for storing the formal version of the FPGA. The invention also provides a method for updating the single plate on line. By the single plate and the method for updating the single plate on line, the cost of the single plate is saved, and the FPGA unit of the single plate is updated on line.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a single board and a method for online upgrading of the single board. Background technique [0002] In the field of communication technology, FPGA (Field Programmable Gate Array, Field Programmable Gate Array) has many advantages such as higher density, faster speed, larger capacity, redistribution, etc., but its power failure is volatile The nature determines that its scope of application has some limitations. [0003] There are two main ways to download FPGA, one is FPGA active loading, that is, FPGA actively reads logic from non-volatile memory (usually ROM); the other is passive loading, that is, FPGA waits for the main control device to download it logic. [0004] Another logic device corresponding to FPGA is CPLD (Complex Programmable Logic Device, complex programmable logic device). Although the speed of CPLD is slow and the capacity is small, it is not easy to lose whe...

AI Technical Summary

Problems solved by technology

[0010] Although the above method is flexible, because FPGA is volatile when power off, it is necessary to add a CPLD to realize the initial logic control function

Therefore, the cost of this solution is high, the design is compl

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