Chip power-on reset circuit and method thereof

Abstract

The invention relates to an integrated circuit and discloses a chip power-on reset circuit and method thereof. In the invention, the chip power-on reset circuit comprises a pre-charge module, a charge charging and discharging module, a wave shaping module and a forced response module, wherein the pre-charge module is used for controlling the charging current of the charge charging and dischargingmodule; the charge charging and discharging circuit transforms the charging current into charging voltage and outputs the charging voltage; the wave shaping module amplifies and shapes the charging voltage to generate a POR (Power-On-Reset) signal; and the forced response module monitors the POR signal in the whole process and generates an output signal to lock and control the pre-charge module. Because the chip power-on reset circuit can generate the POR signal under the condition that the power voltage raises very slowly, after the power voltage is stable, the own power consumption is equalto zero.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a chip power-on reset circuit in the integrated circuit. Background technique [0002] In order to ensure that the integrated circuit can operate normally after the power is turned on normally, a chip power on reset (Power On Reset, referred to as "POR") circuit is indispensable in the system-on-chip (System on Chip, referred to as "SoC") design. Generally speaking, due to the limitation of chip pin resources and cost factors, most of the power-on reset circuits are integrated inside the chip. The chip power-on reset circuit can automatically judge whether the power-on voltage of the chip is normal, and at the same time generate A reset signal, which can be maintained for a period of time to initialize the logic state of the digital circuit inside the chip, so that the digital circuit inside the chip can work normally and reliably after the system is powered on normally. [0003] Therefo...

AI Technical Summary

Problems solved by technology

Therefore, the chip power-on reset circuit proposed by this solution cannot achieve zero power consumption after the power supply is stable. In order to reduce the current, the area can only be increased, so that the advantages of the circuit are no longer obvious

[0007] It can be seen that in the current chip power-on reset circuit, when the power supply voltage is stable, the chip will inevitably consume current when it is working normally, which increases the power consumption of the system.

If the larger power consumption is avoided by increasing the area, the cost will increase

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