Power electronic circuit

Abstract

A power electronic circuit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a first capacitor, a second capacitor, a first inductor, and a second inductor; the first capacitor and the second capacitor are serial connected between an input positive bus and an input negative bus, where the first capacitor and the second capacitor are connected to a fifth node; the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are serial connected between the first capacitor and the second capacitor; the first switching transistor and the second switching transistor are connected to a first node; the second switching transistor and the third switching transistor are connected to a second node, and the third switching transistor and the fourth switching transistor are connected to a third node; the fifth switching transistor and the sixth switching transistor are connected to a fourth node, and the fifth switching transistor is connected to the first node through the first inductor; the sixth switching transistor is connected to the third node through the second inductor; the second node is connected to the fifth node. The embodiments of the present invention avoid long charging and discharging paths of the junction capacitor of the switching transistors.

Description

technical field [0001] The invention relates to the technical field of power electronic systems, in particular to a power electronic circuit. Background technique [0002] Existing power electronic circuits, such as three-level inverters, include four switching tubes—first, second, third, and fourth switching tubes Q1, Q2, Q3, and Q4—connected in series at the positive and negative ends of the DC bus in sequence. Each switch tube has a driving control signal. [0003] During the positive half cycle of the inverter output voltage, the second switching tube Q2 is controlled to be normally on, the fourth switching tube Q4 is normally closed, and the first switching tube Q1 and the third switching tube Q3 are turned on in accordance with SPWM complementarity and their dead zone is guaranteed. [0004] During the negative half cycle of the output voltage, the third switching tube Q3 is controlled to be normally on, the first switching tube Q1 is normally off, and the fourth swit...

AI Technical Summary

Problems solved by technology

[0006] Since one of the charging paths involves three series-connected switching tubes, the loop path is long, and the reverse recovery characteristics of the anti-parallel diode of the first switching tube Q1 have a great influence on the voltage spike of the third switching tube Q3

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