Electrical connection for chip scale packaging
A technology of dielectric layers and devices, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as thermal expansion coefficient mismatch
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[0031] The making and using of this embodiment are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the embodiments.
[0032] Embodiments are described with respect to embodiments in a specific context (ie, post-passivation interconnects below contact lower metallization layers). However, embodiments may also be applied to other metallization layers.
[0033] Now, refer to figure 1 , shows a portion of a semiconductor die 100, including: a semiconductor substrate 101, a metallization layer 103, a contact pad 105, a first passivation layer 107, a second passivation layer 109, a post passivation interconnect (PPI ) 111 , PPI opening 108 , third passivation layer 113 , under-contact metallization (UCM) 115 and ...
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