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Electrical connection for chip scale packaging

A technology of dielectric layers and devices, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as thermal expansion coefficient mismatch

Active Publication Date: 2016-12-14
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This type of thermal expansion coefficient mismatch can cause problems if the semiconductor die is subjected to elevated temperatures

Method used

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  • Electrical connection for chip scale packaging
  • Electrical connection for chip scale packaging
  • Electrical connection for chip scale packaging

Examples

Experimental program
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Embodiment Construction

[0031] The making and using of this embodiment are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the embodiments.

[0032] Embodiments are described with respect to embodiments in a specific context (ie, post-passivation interconnects below contact lower metallization layers). However, embodiments may also be applied to other metallization layers.

[0033] Now, refer to figure 1 , shows a portion of a semiconductor die 100, including: a semiconductor substrate 101, a metallization layer 103, a contact pad 105, a first passivation layer 107, a second passivation layer 109, a post passivation interconnect (PPI ) 111 , PPI opening 108 , third passivation layer 113 , under-contact metallization (UCM) 115 and ...

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PUM

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Abstract

Systems and methods for providing post passivation openings and under-contact metallization are provided. Embodiments include an opening through the rear passivation layer, the opening having a first dimension and a second dimension, the first dimension being greater than the second dimension, wherein the first dimension is aligned perpendicular to a direction of a coefficient of thermal expansion mismatch of the chips. By shaping and aligning the openings through the rear passivation layer in this manner, the rear passivation layer helps protect the underlying layers from stresses generated by mismatches in the coefficients of thermal expansion of the materials. The invention also provides electrical connections for chip scale packaging.

Description

technical field [0001] The present invention relates generally to the field of semiconductors, and more particularly to electrical connections for chip scale packaging. Background technique [0002] Typically, a semiconductor die can be connected to other devices external to the semiconductor die through a type of packaging that utilizes solder bumps. Solder bumps may be formed by first forming an under-contact metallization layer on the semiconductor die and then placing solder over the under-contact metallization layer. After the solder has been placed, a reflow operation may be performed to shape the solder into the desired bump shape. Then, the solder bump can be placed in physical contact with the external device, and another reflow operation can be performed to bond the solder bump with the external device. In this manner, physical and electrical connections can be made between the semiconductor die and an external device (such as a printed circuit board, another sem...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L21/60
CPCH01L23/3157H01L23/525H01L24/05H01L24/06H01L24/13H01L2224/0401H01L2224/05008H01L2224/05012H01L2224/05022H01L2224/05541H01L2224/05552H01L2224/05555H01L2224/05569H01L2224/05572H01L2224/061H01L2224/06137H01L2224/06179H01L2224/141H01L2924/00014H01L2924/00012H01L2924/206
Inventor 游明志林文益李福仁林柏尧
Owner TAIWAN SEMICON MFG CO LTD