A method for distributing multiple interrupt, a interrupt request signal distributing circuit, and a on-chip system

Abstract

In the power control method used for an on-chip system, at least one output of a first wake-up request signal and a second wake-up request signal is controlled in such a way that a time interval between the outputs of the wake-up request signals is same or larger than a time interval threshold value. The first wake-up request signal and the second wake-up request signal are one of concurrent wake-up request signal or continuous wake-up request signals.

Description

technical field [0001] Example embodiments generally relate to multi-processor and / or multi-core systems, eg, methods of spreading multiple interrupts, interrupt request signal spreading circuits, and system-on-chip (SOC) including the same. Background technique [0002] Conventional electronic devices include interrupt controllers for interrupt handling operations. When multiple interrupt sources generate multiple interrupts, the interrupt controller may prioritize the interrupts and provide an interrupt request signal to the processor. An interrupt request signal is generated based on the interrupt. [0003] Recently, as electronic devices have become smaller and lighter, systems on a chip (SOC) have been more widely used in electronic devices. Here, the SOC may include multiple intellectual property (IP) blocks and multiple processors (or processors with multiple cores). [0004] In SOCs, processors often enter low-power modes to reduce power consumption. Each process...

AI Technical Summary

Problems solved by technology

However, if a processor substantially wakes from a low power mode at the same or substantially the same time (eg, sometimes called a sudden wake), there may be an inrush current in the processor

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