DDR series pcb timing compensation method, system and terminal

Abstract

The invention provides a double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal which is applied to the field of signal processing. The method comprises the steps of testing timing sequence deviation time of synchronizing signals of board distribution design of a pcb, testing actual timing sequence deviation time of the synchronizing signals on the pcb, correcting the timing sequence deviation time of the synchronizing signals of the board distribution design of the pcb according to the actual timing sequence deviation time of the synchronizing signals on the pcb, determining the minimum single time-delay circuit number required to be set of a master control end by combining actually-measured delay time of single time-delay circuits and the actual timing sequence deviation time of the synchronizing signals on the pcb, and setting time-delay circuits at the master control end by combining the minimum single time-delay circuit number at the master control end and the timing sequence deviation time of the synchronizing signals of the board distribution design of the pcb after correction. The ddr series pcb timing sequence compensation method, system and terminal can effectively reduce probability of unsynchronized transmission of signals on a data line caused by a difference of pcb wiring.

Description

technical field

[0001] The invention belongs to the field of signal processing, and in particular relates to a timing compensation method, system and terminal of a ddr series pcb board. Background technique

[0002] With the development of embedded electronic products, the current multimedia processor can already run a high frequency to meet the increasing application requirements of the operating system, such as the memory arm-context a9 with a frequency of 1.2Ghz can realize intelligent operation The various application requirements of the system meet the needs of the current embedded intelligent operating system.

[0003] However, in order to meet the large memory and low cost requirements of the operating system at the same time, the current market generally chooses double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, ddr), ddr2 and ddr3, which are fast, large in capacity and low in cost. system memory. However, due to the relatively fast ...

Images