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A system for detecting security performance of security chip under induced error attack

A security chip and error attack technology, applied in the direction of platform integrity maintenance, internal/peripheral computer component protection, etc., can solve problems such as limited effectiveness of security measures, leakage of confidential data, etc.

Active Publication Date: 2016-08-24
SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the security measures adopted by this scheme have limited effects. If the security chip itself has design flaws, the security risks caused by the design flaws may lead to the leakage of confidential data under side-channel attacks.

Method used

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  • A system for detecting security performance of security chip under induced error attack
  • A system for detecting security performance of security chip under induced error attack
  • A system for detecting security performance of security chip under induced error attack

Examples

Experimental program
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Effect test

Embodiment 1

[0052] This embodiment provides a system for detecting the security performance of security chips under induced error attacks, such as figure 1 shown, including:

[0053] The control unit 13 controls the encryption and decryption functional unit 11 in the security chip to perform a decryption operation under an error-induced attack.

[0054] The result analysis unit 12 reads the operation result of the encryption and decryption functional unit 11 and compares it with the built-in reference result, and outputs the analysis result.

[0055] The control unit 13 and the result analysis unit 12 in this embodiment can be arranged inside the security chip or outside the security chip. Regardless of whether it is arranged inside or outside the security chip, as long as there is signal transmission with the encryption and decryption functional unit 11 in the security chip, the corresponding functions can be realized.

[0056] The system for detecting the safety performance of the sec...

Embodiment 2

[0068] On the basis of Embodiment 1, the system for detecting the security performance of the security chip under the detection-induced error attack described in this embodiment, such as figure 1 As shown, the control unit 13 is further configured to control the attack device 2 to stop the round of induced error attack after the encryption and decryption functional unit 11 completes the decryption operation; and trigger the attack device 2 to detect the analysis result , if the analysis result is an error identification, the coordinates of the attacking device 2 locating the location of this round of induced error attack on the security chip are the fault point coordinates.

[0069] The display control unit 4 is also used to control the display device to display the fault point coordinates.

[0070] Therefore, this embodiment provides a system that can effectively detect the security performance of the security chip, and can locate and evaluate the weaknesses of the security c...

Embodiment 3

[0072] On the basis of embodiment 1 or embodiment 2, the system described in this embodiment detects the safety performance of security chips under induced error attacks, such as figure 1 and Figure 4 shown, also includes:

[0073] The self-resetting unit 14 is configured to reset the encryption and decryption functional unit 11 , the result analysis unit 12 and the control unit 13 .

[0074] The control unit 13 is also used to control the encryption and decryption functional unit 11 to start a decryption operation after the encryption and decryption functional unit 11 is reset, and at the same time control the shift of the attack device 2 to the next attack point. Conduct a new round of induced error attacks.

[0075]Therefore, the system for detecting the security performance of the security chip under the induced error attack described in this embodiment can remove the soft error generated by the previous induced error attack through the self-resetting unit 14, so that i...

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Abstract

The invention relates to a system for detecting the safety performance of a safety chip under induced error attacks. The system comprises a control unit, a result analysis unit and an attack device, wherein the control unit controls a safety chip encryption and decryption functional unit to carry out encryption and decryption calculation under the induced error attacks; the result analysis unit reads a encryption and decryption calculation result and compares the result with a built-in reference result; the attack device performs the induced error attacks on the safety chip under the control of the control unit. Therefore, the safety chip and the attack device are combined together through the control unit, the calculation result, under the induced error attacks, of the encryption and decryption functional unit is analyzed through the result analysis unit, and after an error is caused on the encryption and decryption calculation result, the attack device is controlled by the control unit to position coordinates of the positions, on the safety chip, of the induced error attacks as fault point coordinates, so that the system effectively detects the safety performance of the safety chip and positions the fault points.

Description

technical field [0001] The invention relates to a detection system for the safety performance of a safety chip. Specifically, it is a system for detecting the security performance of security chips under induced error attacks. Background technique [0002] In the field of information security applications, security chips based on specific cryptographic algorithms can provide confidentiality and integrity protection for sensitive information. In the prior art, security chips are widely used in electronic products, such as smart cards, RFIDs, USB Keys, and the like. The functions of the security chip mainly include: safe storage of data, data encryption and decryption, digital signature and authentication, and identity authentication. The realization of the above functions depends on modern cryptographic algorithms, including public key cryptographic algorithms, block cipher algorithms, and stream cipher algorithms. Public-key cryptographic algorithms are mainly used for di...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F21/57
CPCG06F21/72G06F21/76
Inventor 邵翠萍李慧云徐国卿
Owner SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI
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