Automatic monitoring closing timer circuit for JTAG (joint test action group) simulator

Abstract

The invention provides an automatic monitoring closing timer circuit for a JTAG (joint test action group) simulator. The circuit comprises a monitoring timer U1, an or gate U2C and a JTAG connector slot TJ1; a watchdog output pin #WDO of the monitoring timer U1 is connected to one input end of the or gate U2; the other input end of the or gate U2 is connected to the pin 6 of the TJ1 and is connected with one end of a resistor R5 at the same time; the other end of the resistor R5 is grounded; the output end of the or gate U2 is connected with one end of a resistor R4 of which the other end is connected with a manual reset pin #WR of the monitoring timer U1; when the JTAG simulator is accessed in a circuit and is debugged, the pin 6 and the pin 5 of a connector of the JTAG simulator are connected and are inserted into JTAG connector slot TJ1 of the automatic monitoring closing timer circuit for the JTAG simulator, the monitoring timer automatically closes a watchdog circuit, a system electrifying resetting function is reserved ,and the operation of the debugging stage is simplified.

Description

technical field [0001] The invention relates to the design of a monitoring timer circuit of a high-reliability main board, in particular to a JTAG emulator automatically closing the monitoring timer circuit. Background technique [0002] With the development of aerospace electronic products, military electronic products and high-reliability industrial applications to high-speed circuits, a large number of CPUs or DSPs with JTAG functions are used as the motherboard platform. In order to ensure that the system can be reset in time when the system is disturbed, it is usually designed with The watchdog timer circuit (watchdog) is fed by the application program during the watchdog period. Since the conventional watchdog application circuit will also work during the debugging process, if the application program does not feed the dog in time, it will Functional devices that cause the watchdog circuit to reset the entire printed board and need to be reset (such as CAN bus protocol ...

AI Technical Summary

Problems solved by technology

However, developers cannot guarantee to feed the dog in time during the software or system debugging stage, especially when performing similar single-step tracking operations, which will cause the watchdog to function and cause the system to reset.

Generally speaking, after some CPU / DSP types are taken over by JTAG, the reset signal will not affect the operation of the CPU / DSP, but it will definitely affect other chips or modules connected to the reset function on the board. If the dog is not fed in time during the debugging process, it will Cause debugging failure. In practical applications, the debugging problem of the watchdog is often solved by jumping the pin to disconnect the timer or unplugging the monitoring timer, such as image 3 As shown, if the monitoring timer is unplugged, the monitoring timer will lose the power-on reset system function, which will increase the complexity of debugging

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