A configuration file loading device and method
A configuration file and loading device technology, applied in the circuit field, can solve problems such as board function failure, system process failure, configuration file loading failure, etc., and achieve the effect of improving efficiency
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Embodiment 1
[0026] refer to figure 2 , shows a loading device of a configuration file of the present application, including: FPGA chip 204 and MCU202, the FPGA chip 204 is used to establish a PCIe link between the MCU202 and the FPGA chip 204 after the FPGA chip 204 is powered on , so as to load the configuration file through the PCIe link; after determining that the establishment of the PCIe link fails, trigger the reset of the MCU2024; obtain the configuration file from the MCU202 through the data bus between the MCU202 and the FPGA chip 204, and load the configuration file.
[0027] In the prior art, when the establishment of the PCIe link fails, the configuration file of the FPGA chip needs to be reloaded by resetting the board or returning it to the factory for maintenance. In this embodiment, when the establishment of the PCIe link fails, the configuration file is obtained through the data bus between the MCU and the FPGA chip, without resetting the board or returning it to the fac...
Embodiment 2
[0033] refer to Figure 4 , shows a configuration file loading device of the present application. The device in this embodiment can automatically switch the loading mode. When the PCIe loading method fails, the board can automatically load the configuration file through the Slave SelectMAP method without requiring the board reset the card or return it to the factory for repair. like Figure 4As shown, the device includes: MCU, FPGA chip, SPIFlash and tri-state chip. Wherein, the MCU is connected to the FPGA chip, the FPGA chip is connected to the SPI flash, the output terminal of the tri-state chip is connected to the mode configuration pin of the FPGA chip, and the input of the tri-state chip is the first instruction information sent by the FPGA chip. The first indication information is used to indicate whether the PCIe link is successfully established. The first indication signal can be a link_ok signal, which can be used as a POR signal of the MCU and a chip with a low-le...
Embodiment 3
[0041] refer to Figure 5 , shows a method for loading a configuration file in the present application, the method can be executed by the device in the above device embodiment, for example, executed by the FPGA chip in the above device embodiment, therefore, the features in the above device embodiment are all can be combined into this embodiment. like Figure 5 As shown, the method includes:
[0042] Step 502, after the FPGA chip is powered on, establish a PCIe link between the MCU and the FPGA chip, so as to load configuration files through the PCIe link;
[0043] Step 504, when the PCIe link fails to be established, the MCU is triggered to reset;
[0044] In a preferred example of the embodiment of the present invention, when the PCIe link fails to be established, a low-level first indication signal may be sent to the MCU, where the first indication signal is used to trigger the MCU to reset. For example, the first indication signal may be a link_ok signal, and the link_...
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