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Chip stack with electrically insulating walls and method of form chip stack

A technology of chip stacking and electrical insulating materials, applied in the direction of circuits, electrical components, electrical solid devices, etc.

Active Publication Date: 2014-07-23
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] These constraints often lead to limits on allowable power distribution and stack height in 3D chip stacks due to the thermal resistance of the microbump bonding layer(s)

Method used

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  • Chip stack with electrically insulating walls and method of form chip stack
  • Chip stack with electrically insulating walls and method of form chip stack
  • Chip stack with electrically insulating walls and method of form chip stack

Examples

Experimental program
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Embodiment Construction

[0017] It is desired to significantly increase the fraction of solder area existing between chips in a chip stack, so as to reduce the vertical thermal resistance between the chips and at the same time avoid solder bridging between micro bumps.

[0018] The description provided below relates to a 3D chip stack in which an insulating guide structure (ie "wall") is formed on one or both of the main chip surface. The wall will significantly reduce or prevent misalignment of solder joint material and hinder bridging between adjacent pads. This will bring the ability to increase the area of ​​the micro bumps, and increasing the area of ​​the micro bumps will significantly reduce the vertical thermal resistance in the chip stack.

[0019] reference figure 1 , Provides a method for forming a chip stack. Such as figure 1 As shown in, the method initially involves arranging the solder pads 10 along the plane of one of the two major surfaces (ie, the “top surface”) 11 of the substrate 12. ...

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PUM

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Abstract

The invention relates to a chip stack with electrically insulating walls and a method of form the chip stack. The method of forming the chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Description

Technical field [0001] The present invention relates to chip stacking, and more specifically, to a 3D chip stacking with electrically insulating walls between microbumps. Background technique [0002] In a 3D chip stack, chips such as integrated circuits are stacked one on top of the other in a three-dimensional stack with electrical interconnections between the layers. This configuration has many advantages, for example, it provides designers with the ability to place an increased number of chips in a given two-dimensional area with increased electrical communication between the chips. Since there is no thermal expansion mismatch between silicon chips, finer pitches such as micro bumps with a density of more than 10,000 per square centimeter can be used ( < / =100 microns) electrical interconnection. However, this 3D chip stack is more difficult to cool sufficiently than a planar array of individual chips. [0003] Recently, it has been observed that the thermal resistance of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/60H01L25/16
CPCH01L24/13H01L2224/10126H01L2224/10145H01L2224/13H01L2924/3841H01L2924/00012
Inventor E·G·科尔根罗载雄
Owner IBM CORP