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A method and system for realizing nvme protocol multi-command queue

A technology of command queue and implementation method, applied in the direction of electrical digital data processing, instrument, input/output to record carrier, etc., can solve the problem that the NVME protocol cannot actually support multiple command queues, etc.

Active Publication Date: 2018-02-06
RAMAXEL TECH SHENZHEN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] For the above defects, the purpose of the present invention is how to solve the problem of multi-command queues that the NVME protocol cannot actually support due to the limitation of storage space

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  • A method and system for realizing nvme protocol multi-command queue
  • A method and system for realizing nvme protocol multi-command queue
  • A method and system for realizing nvme protocol multi-command queue

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Embodiment Construction

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0015] figure 2 It is a system block diagram for implementing multi-command queues of the NVME protocol. Compared with the implementation method of separately opening up space for command queues, the present invention stores all acquired commands in a unified command storage area; at the same time, open up space as a queue information table to save each command Information about the queue.

[0016] The relevant information of each command queue is stored in the q...

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Abstract

The invention discloses a method for realizing a multi-command queue of the NVME protocol. The commands and queue information of the command queue are stored separately, and a unified command storage cache is set to store the specific commands corresponding to the elements of each command queue and the queue numbers corresponding to the commands. Set the queue information table to store the queue information of each queue currently existing on the Host side. When the SSD controller executes specific commands in sequence, it searches the corresponding queue information from the queue information table according to the queue number corresponding to the specific command. At the same time, a system for implementing NVME protocol multi-command queue is also implemented. By actively reading commands from the command queue at the Host side, a unified command storage area is opened inside the controller to store these commands, and the command queue information is obtained by looking up the table when executing commands. The advantage of this is that the storage resources consumed by adding a command queue to the control chip are very small, and can support a very large number of command queues, which can greatly improve IOPS.

Description

technical field [0001] The invention relates to NVME protocol optimization, in particular to an implementation method and system for expanding the NVME protocol multi-command queue. Background technique [0002] NVME is a scalable host controller interface with PCIe SSDs designed for enterprise and client systems, including an optimized register interface and command set. Fundamentally speaking, NVME is an optimized queue interface. The host submits commands to the queue, and the queue completes the reading or writing of data, not in the order of the host command submission time. Moreover, it has a component dedicated to managing queues to complete operations such as queue creation, deletion, command termination, and security. In the existing solid-state drive control chip, the NVME protocol breaks the bottleneck of IOPS (Input / Output Operations Per Second, that is, the number of read and write (I / O) operations per second) due to its low latency, energy saving, and CPU perf...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F13/38
Inventor 黄毅黄运新董剑
Owner RAMAXEL TECH SHENZHEN
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