Parallel pseudo CSD encoder for variable coefficient multiplier

Abstract

The invention relates to the technical field of integrated circuits, in particular to a parallel pseudo CSD encoder for a variable coefficient multiplier. The parallel pseudo CSD encoder comprises an arithmetic logic circuit and an output logic circuit. The input end of the arithmetic logic circuit is connected with external input data, and the output end of the arithmetic logic circuit is connected with the first input end of the output logic circuit. The second input end of the output logic circuit is connected with external input data, and the output end of the output logic circuit is connected with the coefficient input end of a backward-stage multiplier. The parallel pseudo CSD encoder has the advantages that it is ensured that a code system formed after pseudo CSD encoding has the same nonzero digit number as a traditional CSD encoding, and meanwhile the parallel arithmetic logic is adopted to eliminate carry transmission logic produced in the traditional CSD encoding process, so that the pseudo CSD encoder arithmetic speed is increased, the parallel pseudo CSD encoder is unrelated with the binary digit bit length needing to be encoded, the fixed-delay encoding circuit is formed, and the data throughput of the pseudo CSD encoder is greatly improved. The parallel pseudo CSD encoder is especially applicable to variable coefficient multipliers.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a parallel pseudo-CSD encoder used for variable coefficient multipliers. Background technique [0002] Variable coefficient multiplier is a very important basic unit in digital integrated circuits. In digital system design, the parameters of the multiplier largely affect the parameter performance of the entire digital system. In binary multiplication, each non-zero bit of the coefficient generates a partial product, and then all the partial products are accumulated by an adder to obtain the final result. Generally speaking, the multiplier will use the encoder to encode the coefficients, thereby reducing the number of non-zero bits in the coefficients to reduce the generation of partial products, thereby reducing the number of adders, reducing power consumption and area, and improving the performance of the multiplier. purpose of speed. Among them, the CSD (Canonica...

AI Technical Summary

Problems solved by technology

Due to the influence of carry propagation, the delay time of the traditional CSD encoder, the encoding speed is proportional to the bit length N of the binary number, so that the data throughput of the CSD encoder is limited by the number of encoding bits, which in turn restricts the working speed and data of the multiplier. throughput capacity

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