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storage device
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A storage device and wiring technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as memory cell interference
Active Publication Date: 2020-04-24
株式会社PANGEA
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Problems solved by technology
However, if memory cells are further integrated in the future, interference between memory cells may become more pronounced.
Method used
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no. 1 Embodiment approach
[0024] First, the first embodiment will be described.
[0025] figure 1 It is a perspective view showing the storage device of this embodiment.
[0026] figure 2 (a) and (b) are cross-sectional views showing the storage device of this embodiment.
[0027] image 3 (a) and (b) are cross-sectional views showing the memory cell of the memory device of the present embodiment, (a) shows a high resistance state, and (b) shows a low resistance state.
[0028] Figure 4 (a) and (b) are graphs showing drive signals of the storage device of the present embodiment with time taken on the horizontal axis and voltage taken on the vertical axis, (a) shows the setting operation, and (b) shows the reset operation.
[0029] In addition, for the convenience of illustration, figure 1 , figure 2 In (a) and (b), each part is simplified and depicted. In addition, figure 2 (b) shows the YZ plane including the local bit line 31, and the interlayer insulating film 39 on the near side is omitted in order to i...
no. 2 Embodiment approach
[0073] Next, the second embodiment will be described.
[0074] Figure 8 It is a perspective view showing the storage device of this embodiment.
[0075] Picture 9 (a) is a cross-sectional view showing the storage device of this embodiment, and (b) is a cross-sectional view showing the storage unit of the storage device of this embodiment.
[0076] Such as Figure 8 and Picture 9 As shown in (a), the configuration of the storage unit 30 of the storage device 2 of this embodiment is similar to that of the storage device 1 of the first embodiment (see figure 1 )different. That is, in the memory device 2, one row of local word lines 32 extending in the Y direction is arranged in the Z direction between two local bit lines 31 adjacent in the X direction. Therefore, in a certain XZ section, the local bit lines 31 and the local word lines 32 are alternately arranged in the X direction.
[0077] Furthermore, a GeSbTe layer 36 as a resistance change layer is provided on the entire surface ...
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PUM
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Abstract
Embodiments of the present invention provide a memory device with less interference between memory cells. The memory device according to the embodiment includes: first wiring extending in a first direction; second wiring extending in a second direction intersecting the first direction; and a first layer provided on the first direction. 1 at least a part of the surface of the wiring; a second layer provided on at least a part of the surface of the second wiring; and a third layer provided between the first wiring and the second wiring. between the lines and in contact with the first layer and the second layer. The first layer contains the first element of Group 14, the second layer contains the second element of Group 15 and the third element of Group 16, and the third layer contains the first element, the the second element and the third element.
Description
[0001] [Related Application Case] [0002] This application enjoys priority based on Japanese Patent Application No. 2015-71446 (application date: March 31, 2015). This application contains all the contents of the basic application by referring to the basic application. Technical field [0003] The embodiment of the present invention relates to a storage device. Background technique [0004] In recent years, a storage device in which storage units are three-dimensionally integrated has been proposed. In such a memory device, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction are provided, and memory cells are connected between each word line and each bit line. Then, by applying a specific voltage between one word line and one bit line, one memory cell connected therebetween is selected, and data is written to or read from the memory cell. However, if memory cells are made more integrated in the future, interferenc...
Claims
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Application Information
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