Fin Patterning Method for Increasing Process Margin

Abstract

The present invention provides a fin patterning method for increasing process margin. A method of manufacturing a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on a sidewall of each first spacer. In some embodiments, the spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of adjacent first spacers physically merge to form a merged second spacer. A second spacer cutting process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of the plurality of third spacers is formed on a sidewall of each second spacer. A third spacer cutting process may be performed to selectively remove at least one third spacer. A first etching process is performed on the substrate to form fin regions. The plurality of third spacers masks a portion of the substrate during the first etching process.

Description

technical field [0001] The present invention relates to a fin patterning method for increasing process margin. Background technique [0002] The electronics industry experiences a continuously increasing demand for smaller and faster electronic devices, which are simultaneously capable of supporting a greater number of increasingly complex and sophisticated functions. Accordingly, a continuing trend in the semiconductor industry is to manufacture low cost, high performance, and low power integrated circuits (ICs). To date, most of these goals have been achieved by scaling down semiconductor IC dimensions (eg, minimum feature size) and thereby increasing production efficiency and reducing associated costs. However, these scaling downs also increase the complexity of the semiconductor manufacturing process. Accordingly, the realization of continued advances in semiconductor ICs and devices also requires similar advances in semiconductor manufacturing processes and technologi...

AI Technical Summary

Problems solved by technology

Therefore, current lithography tools do not provide sufficient process margin, especially when using existing lithography processes

As a result, the FinFET critical dimension (CD) can be directly impacted by pattern misalignment or other lithography errors, which can lead to degraded device performance and / or device failure

Therefore, existing technologies cannot be fully satisfactory in all respects

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