3d NAND memory and its formation method

Abstract

A 3D NAND memory and its forming method. The forming method of the 3D NAND memory of the present invention directly forms a stacked structure of a control gate and an isolation layer on a semiconductor substrate. After forming a storage structure in the stacked structure, etching In the top selection gate layer, the top selection gate layer is disconnected into several top selection gates, and the 3D NAND memory is correspondingly divided into several storage blocks through the disconnected top selection gates. Therefore, the 3D NAND memory storage of the present application Blocks are divided by disconnecting several top-layer select gates, and there is no need to form gate spacers in the stacked structure for the division of different memory blocks, thus avoiding fluctuations in the characteristic dimensions of the gate spacers and simplifying the process steps.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the substrate; in ...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the gate spacers between the memory blocks generally pass through the stack structure in the vertical direction, and the gate spacers on both sides of the pseudo-common source The sidewall (Gate Line Slit, GLS) corresponding to the exposed pseudo common source is separated, but in the manufacturing process of the existing 3D NAND memory, the characteristic size of the gate spacer is easy to fluctuate, which affects the performance of the memory

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