Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes

A check node and node technology, applied in the application of error detection coding of multiple parity bits, error correction/detection, and coding using block codes, to achieve the effect of no performance loss and reduced computational complexity

Pending Publication Date: 2020-04-10
UNIVERSITY OF SOUTHERN BRITTANY
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Problems solved by technology

However, computation and ordering of syndromes introduces high complexity that increases with the number of messages processed by check node processing units, thus limiting the usefulness of syndrome-based architectures for messages with processing High code rate applications with high values ​​of

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  • Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes
  • Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes
  • Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes

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Embodiment Construction

[0082] Embodiments of the invention provide apparatus, methods and computer program products for decoding a signal encoded using at least one error correcting code with reduced computational complexity and reduced latency. In particular, they provide efficient pre-ordering techniques and check node processing architectures implemented in iterative decoders for decoding signals encoded with at least one non-binary error-correcting code.

[0083] Methods, devices and computer program products according to various embodiments may be implemented in several types of digital data transmission and storage devices and systems for use in several types of applications. Exemplary devices and systems include, but are not limited to, computers, diskettes, laptops, telephones, smartphones, tape recorders, base stations, drones, satellites, and the like. Exemplary applications include magnetic and optical recording, digital television and video broadcasting, digital communications, and the l...

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Abstract

Embodiments of the invention provide a check node processing unit (25-cn) configured to determine at least two check node messages in an Extended Min-Sum, EMS, decoder to decode a signal encoded usinga Non-Binary LDPC, NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units (24-cn) configured to determine at least three permuted variable node messages by permuting at least three variable node messages generated by one or more variable node processing units (23), each variable node message comprising components, a component comprising a symbol and a reliability metrics associated with said symbol; a syndrome sub-check node (31) configured to determine check node messages from a set of syndromes, the set of syndromes being determined fromone or more intermediate messages computed from the at least three permuted variable node messages; a forward-backward sub-check node (32) configured to determine permuted check node messages at least from one of said one or more intermediate messages; a switching unit (33) configured to generate each check node message of a given index from the check node messages determined by the at least onesyndrome sub-check node (31) or from the permuted check node messages determined at the at least a forward-backward sub-check node (32) depending on said given index.

Description

technical field [0001] The present invention relates generally to digital communications, and in particular to methods and apparatus for decoding signals encoded using error correcting codes. Background technique [0002] Error correcting codes are implemented in a variety of data processing systems and devices to ensure that data is protected from errors introduced during data transmission or storage in the presence of noise and / or interference. Encoding involves adding redundant data to the original data, which enables detection and / or correction of errors. [0003] Error correcting codes are implemented in a large number of devices and systems that have applications, eg, in data communications and / or storage. Exemplary applications include voice and multimedia transmission, e.g. in wireless ad hoc networks (e.g. standardized in Wi-Fi 802.11), in radio communication systems (e.g. in 3G, 4G / LTE, 5G and later, etc.) , in optical communication systems, and in digital video ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/1117H03M13/1171H03M13/1131
Inventor C·马尔尚E·布蒂永
Owner UNIVERSITY OF SOUTHERN BRITTANY
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