Open-drain output control circuit

Abstract

The invention discloses an open-drain output control circuit. The circuit comprises a first MOS tube and a second MOS tube, a first resistor, a third MOS tube, and a second resistor. The first MOS tube and the second MOS tube are electrically connected between a first power supply voltage and a reference potential; grid electrodes of the first MOS tube and the second MOS tube are connected with aDRV unit, and the DRV unit receives a first enable signal. The first resistor and the third MOS tube are electrically connected between a second power supply voltage and the reference potential, a grid electrode of the third MOS tube is connected with drain electrodes of the first MOS tube and the second MOS tube, and a drain electrode of the third MOS tube outputs a second enable signal. The second resistor is connected between the grid electrode and the drain electrode of the third MOS tube and is used for clamping the second enable signal within a preset voltage range when the first power supply voltage is lower than an undervoltage locking voltage. According to the invention, on the basis of a method of bridging the resistor on the third MOS tube, a high-level fault when the output enable signal FLAG is powered on along with the first power supply voltage can be eliminated, the output enable signal FLAG is clamped near the Vgs voltage, so that false triggering of FLAG output is avoided.

Description

technical field [0001] The invention belongs to the technical field of open-drain circuits, and in particular relates to an open-drain output control circuit. Background technique [0002] In integrated circuits, open drain (OD, open drain) circuits or open collector (OC, open collector) circuits are often used, where "drain" and "collector" correspond to the drain of the MOS transistor and the collector of the triode, respectively. The open-drain circuit refers to a circuit with the drain of the MOS tube as the output terminal, which can convert the control signal under a certain power supply voltage into a signal under another power supply voltage, and is often used for signal transmission between different power supply modules in power management chips . [0003] ginseng figure 1 Shown is the circuit schematic diagram of the open-drain output control circuit in the prior art, which includes PMOS transistor MP1, NMOS transistor MN1, NMOS transistor M1 and pull-up resisto...

AI Technical Summary

Problems solved by technology

[0006] Whether VCC2 is powered on before VCC1 or VCC2 and VCC1 are powered on at the same time, the output enable signal FLAG has an undesired high-level fault, which may cause false triggering of the FLAG output

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