Open-drain output control circuit

Abstract

The present invention discloses an open-drain output control circuit. The open-drain output control circuit includes: a first MOS transistor and a second MOS transistor, electrically connected between the first power supply voltage and a reference potential, the first MOS transistor and the second MOS transistor. The gate of the second MOS transistor is connected to the DRV unit, and the DRV unit receives the first enabling signal; the first resistor and the third MOS transistor are electrically connected between the second power supply voltage and the reference potential, and the third MOS transistor The gate of the gate is connected to the drains of the first MOS transistor and the second MOS transistor, and the drain of the third MOS transistor outputs the second enable signal; the second resistor is connected between the gate and the drain of the third MOS transistor , for clamping the second enable signal within a preset voltage range when the first power supply voltage is lower than the undervoltage lockout voltage. The present invention can eliminate the high-level fault of the output enable signal FLAG when the first power supply voltage is powered on by connecting the resistance on the third MOS tube, clamp the output enable signal FLAG near the Vgs voltage, and avoid The FLAG output is falsely triggered.

Description

technical field [0001] The invention belongs to the technical field of open-drain circuits, and in particular relates to an open-drain output control circuit. Background technique [0002] In integrated circuits, open drain (OD, open drain) circuits or open collector (OC, open collector) circuits are often used, where "drain" and "collector" correspond to the drain of the MOS transistor and the collector of the triode, respectively. The open-drain circuit refers to a circuit with the drain of the MOS tube as the output terminal, which can convert the control signal under a certain power supply voltage into a signal under another power supply voltage, and is often used for signal transmission between different power supply modules in power management chips . [0003] ginseng figure 1 Shown is the circuit schematic diagram of the open-drain output control circuit in the prior art, which includes PMOS transistor MP1, NMOS transistor MN1, NMOS transistor M1 and pull-up resisto...

AI Technical Summary

Problems solved by technology

[0006] Whether VCC2 is powered on before VCC1 or VCC2 and VCC1 are powered on at the same time, the output enable signal FLAG has an undesired high-level fault, which may cause false triggering of the FLAG output

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