Manufacturing method of step structure, manufacturing method of 3D NAND memory device and 3D NAND memory device
A technology of 3D NAND and storage devices, which is applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of complex step structure, cumbersome process of trimming and etching, etc., and achieve the reduction of driving resistance, save process steps, and reduce the driving force. The effect of time delay
Active Publication Date: 2020-09-22
YANGTZE MEMORY TECH CO LTD
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[0003] However, in the current 3D NAND memory device, as the number of stacked layers increases, the corresponding step structure is more complicated, and the process of trimming and etching is more cumbersome.
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[0069] The inventors have found that when using dual stack technology (dual stack) for stacking design of 3D NAND memory devices, as the number of stacking layers increases, the design of the step structure for driving connections becomes more and more complicated. As the number increases, the process of trimming and etching becomes more complicated; at the same time, if figure 1 As shown, a single storage array in a 3D NAND storage device adopts a single-side drive structure design, that is, it is driven from a stepped structure on one side of the storage array, figure 1 The stepped structures 201 and 202 in the storage array structure 101 are unilaterally driven, figure 1 The step structures 203 and 204 in the storage array structure 102 are unilaterally driven. As the number of stacked layers increases, each layer of the stacked composite layer is designed to be thinner and thinner, corresponding to the drive resistance of the storage block in the storage array structure. ...
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The invention provides a manufacturing method of a step structure, a manufacturing method of a 3D NAND memory device and the 3D NAND memory device. The step structure is arranged in the middle of thestacking structure, comprises a plurality of mutually independent subarea step structures, and can be driven from the middle to the two sides at the same time, thereby reducing resistance generated when the memory blocks are driven, and solving the problem of driving time delay. During the forming of a partition step structure, the method comprises the following steps: trimming and etching an upper half region of a stacked structure; selectively the partial area of the step structure formed in the upper half area of the stacking structure, etching and copying the corresponding step structure to the lower half area of the stacking structure, and forming the complete partition step structure, thereby reducing the trimming and etching process steps, improving the production efficiency, and reducing the production cost is reduced. The auxiliary step introduced in the Y-axis direction can reduce the length of the partition step structure and reduce the number of required masks; the false step structure for separating two adjacent stacked structures is designed into a very steep step, so the occupied area can be reduced.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a stepped structure, a method for manufacturing a 3D NAND storage device, and a 3D NAND storage device. Background technique [0002] 3D NAND storage device is a technology for stacking data units. At present, more than 32 or even 72 layers of data units can be stacked. It overcomes the limitation of the actual expansion limit of planar memory, further increases the storage capacity, and reduces The storage cost of data bits reduces energy consumption. [0003] However, in the current 3D NAND storage device, as the number of stacked layers increases, the corresponding step structure is more complicated, and the process of trimming and etching is more cumbersome. Contents of the invention [0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for manufacturi...
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IPC IPC(8): H01L27/11524H01L27/11551H01L27/1157H01L27/11578H10B41/10H10B41/35H10B41/20H10B41/27H10B41/30H10B41/41H10B41/50H10B43/10H10B43/20H10B43/27H10B43/30H10B43/35H10B43/40H10B43/50
CPCH10B41/10H10B41/20H10B41/30H10B43/10H10B43/20H10B43/30H10B41/50H10B43/50H10B41/27H10B43/27Y02D10/00H10B43/40H10B43/35H10B41/35
Inventor 张中孙中旺周文犀夏志良
Owner YANGTZE MEMORY TECH CO LTD