Chip layout method and device, storage medium and electronic equipment

Abstract

The invention provides a chip layout method and device, a storage medium and electronic equipment, and the method comprises the steps: obtaining a logic diagram executed by a to-be-laid-out chip and an equipment list corresponding to the to-be-laid-out chip; determining a layout diagram of the chip to be laid out based on the logic diagram and the equipment list by utilizing a pre-trained layout model, wherein the layout diagram at least comprises the placement position of each piece of equipment in the chip to be laid out. The pre-trained layout model is used for carrying out chip layout, thelayout diagram of the to-be-laid-out chip can be rapidly obtained through the logic diagram and the equipment list, compared with manual chip layout, the method has the advantages that the consumed time is greatly shortened, and the chip layout efficiency is improved; and moreover, the trained layout model is used for carrying out a large number of machine operations, and compared with manual calculation, the method is high in accuracy, i.e., improves the accuracy of chip layout.

Description

technical field [0001] The present disclosure relates to the technical field of chip design, and in particular, to a chip layout method, device, storage medium and electronic equipment. Background technique [0002] A chip refers to a silicon chip containing an integrated circuit; it is often used as a part of a computer or other electronic equipment due to its low power consumption, small size, and fast operating speed. In the process of producing chips, chip layout is a complex and time-consuming task, because the process involves integrated circuit logic and various devices that implement circuit logic, and it also needs to take into account device attributes and circuit design principles. [0003] At present, professionals who design chips carry out multiple trials, error checking, corrections, and retests based on known logic diagrams to place each device on a certain position on the silicon chip, and then complete the chip layout. Manual layout not only consumes a lon...

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Problems solved by technology

[0004] In view of this, the purpose of the present disclosure is to provide a chip layout method, device, storage medium and electronic equipment, which can avoid the time-consuming manual layout in the prior art, low chip layout efficiency, and The process is complex, prone to omissions, and poor layout accuracy

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