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In-memory compute array with integrated bias elements

A computing array and memory technology, applied in the field of memory arrays, can solve the problems of confusing drawings, no separate marking, etc.

Pending Publication Date: 2020-12-08
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

To avoid confusing the drawings, the image 3 Access transistors are shown in , but are not individually labeled, only wordline reference designators

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  • In-memory compute array with integrated bias elements
  • In-memory compute array with integrated bias elements
  • In-memory compute array with integrated bias elements

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Embodiment Construction

[0044] The present invention can be understood more readily by referring to the detailed description of the invention. The terminology used herein is for the purpose of describing particular embodiments only, and shall not be limiting of the claims, unless the terms are determined to be so by a court or body recognized with jurisdiction. Unless otherwise defined herein, terms used herein shall have their ordinary meanings as known in the relevant art.

[0045] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with electronic circuitry, computing systems (including client and server computing systems, networks, and other related techno...

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Abstract

The embodiment of the invention relates to an in-memory compute array with an integrated bias elements. The in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of biasengines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

Description

technical field [0001] The present disclosure generally relates to memory arrays with in-memory computing capabilities. More particularly, but not exclusively, the present disclosure relates to in-memory computing arrays with integrated bias elements. Background technique [0002] Various computer vision, speech recognition, and signal processing applications are known to benefit from the use of learning machines. As discussed in this disclosure, a learning machine may fall under the technical names of machine learning, artificial intelligence, neural networks, probabilistic inference engines, accelerators, and the like. Such machines are arranged to quickly execute hundreds or thousands of concurrent operations. Conventional learning machines can deliver hundreds of trillions of floating-point operations per second (i.e., millions of million (10 12 ) computing power of floating-point operations). [0003] In some cases, a learning machine is organized with one or more a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C7/18G11C8/10G11C11/418G11C11/419
CPCG11C7/1006G11C7/1051G11C7/18G11C8/10G11C11/418G11C11/419G11C7/1012G11C11/54H10B10/12
Inventor A·格罗弗T·罗伊N·乔拉
Owner STMICROELECTRONICS SRL