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rapidIO interface architecture and data processing method

A technology for data processing and data reception, applied in electrical digital data processing, various digital computer combinations, instruments, etc., can solve problems such as the inability to support deep learning large-scale parallel computing requirements

Active Publication Date: 2021-01-05
ZHUHAI ORBITA AEROSPACE SCI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Deep learning requires massive data parallel computing, and traditional computing architectures cannot support the large-scale parallel computing requirements of deep learning

Method used

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  • rapidIO interface architecture and data processing method
  • rapidIO interface architecture and data processing method
  • rapidIO interface architecture and data processing method

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Embodiment Construction

[0020] The idea, specific structure and technical effects of the present invention will be clearly and completely described below in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, scheme and effect of the present invention.

[0021] In the description of the present invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc. indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only In order to facilitate the description of the present invention and simplify the description, it does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

[0022] In the description of the present invention, several means one or more, and mult...

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Abstract

The invention discloses a rapidIO interface architecture and a data processing method. The interface architecture comprises a rapidIO interface module used for receiving and sending data; a DMA module; a DDR3 memory; a DRR3 controller module which is connected with the DDR3 memory and the DMA module; an ARM9 processor module; an AI co-processing module; an SPARC processor module which is connectedwith the rapidIO interface module; and an AXI4 bridging module which is connected with the rapidIO interface module, the DMA module, the DRR3 controller module, the SPARC processor module, the ARM9 processor module and the AI co-processing module. The requirement of an artificial intelligence chip for high-speed data processing can be met.

Description

technical field [0001] The invention relates to the technical field of artificial intelligence chips, in particular to a RapidIO interface architecture and a data processing method. Background technique [0002] Artificial intelligence will drive a new computing revolution. Deep learning requires massive data parallel computing, and traditional computing architectures cannot support the large-scale parallel computing requirements of deep learning. In order to expand the functionality of a single chip, a heterogeneous multi-core architecture is often adopted. The OAI-18 heterogeneous multi-core artificial intelligence chip designed by Zhuhai Orbit Aerospace Technology Co., Ltd. realizes the structure that the ARM processor and the SPARC processor are on the same chip. It is necessary to design and use the RapidIO interface architecture based on the heterogeneous multi-core artificial intelligence chip in this chip to solve the high-speed data processing requirements of the ...

Claims

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Application Information

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IPC IPC(8): G06F13/28G06F13/38G06F15/17
CPCG06F13/28G06F13/385G06F15/17
Inventor 颜军黄仕林颜志宇龚永红唐芳福韩俊
Owner ZHUHAI ORBITA AEROSPACE SCI TECH CO LTD