Data reuse memory access conflict elimination method for coarse-grained reconfigurable structure

Abstract

The invention discloses a data reuse memory access conflict elimination method for a coarse-grained reconfigurable structure, and provides a loop transformation model which is applied to a perfect nested loop kernel and is used for maximizing effective data reuse so as to maximize available data reuse between iterations in a program running process and a configuration file change strategy in a code generation stage. Redundant memory access operation in a data reuse pair is eliminated, and memory access conflicts in the loop execution process are reduced.

Description

technical field [0001] The present application relates to the field of coarse-grained reconfigurable structure compilers, and in particular, relates to a loop transformation model aimed at maximizing effective data reuse of reconfigurable structures and a configuration file modification strategy used in the code generation phase. Background technique [0002] Coarse-Grained Reconfigurable Architecture (CGRA) is a new hardware architecture with higher energy efficiency. It is mainly used for hardware acceleration of computing-intensive applications, such as video processing and neural network operations. After research and investigation, it is found that the application execution time is mainly consumed in the core part of the program loop. Reference ADRES [1] model gives a typical CGRA structure, such as figure 1 shown. The compiler abstracts the core part of the program loop as a data flow graph (data flow graph, DFG), and maps it to different processing elements (proces...

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Problems solved by technology

However, none of the above studies considered ways to reduce the number of memory access operations to reduce memory access conflicts

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