Data reuse memory access conflict elimination method for coarse-grained reconfigurable structure

A coarse-grained, data technology, applied in the field of coarse-grained reconfigurable structure compilers, which can solve the problem of not considering reducing the number of memory access operations

Active Publication Date: 2021-04-09
SHANGHAI JIAO TONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, none of the above studies considered ways to reduce the number of memory access operations to reduce memory access conflicts

Method used

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  • Data reuse memory access conflict elimination method for coarse-grained reconfigurable structure
  • Data reuse memory access conflict elimination method for coarse-grained reconfigurable structure
  • Data reuse memory access conflict elimination method for coarse-grained reconfigurable structure

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Embodiment Construction

[0089] The following describes the preferred embodiments of the present application with reference to the accompanying drawings to make the technical content clearer and easier to understand. The present application can be embodied in many different forms of embodiments, and the protection scope of the present application is not limited to the embodiments mentioned herein.

[0090] The idea, specific structure and technical effects of the present application will be further described below in order to fully understand the purpose, features and effects of the present application, but the protection of the present application is not limited thereto.

[0091] Such as figure 2 As shown, the schematic diagram of the compiler back-end process of an embodiment of the present application, wherein,

[0092] Step 201, using the CGRA compiler front end based on LLVM (Low Level Virtual Machine) to compile the loop kernel part of the source program into an intermediate representation (in...

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Abstract

The invention discloses a data reuse memory access conflict elimination method for a coarse-grained reconfigurable structure, and provides a loop transformation model which is applied to a perfect nested loop kernel and is used for maximizing effective data reuse so as to maximize available data reuse between iterations in a program running process and a configuration file change strategy in a code generation stage. Redundant memory access operation in a data reuse pair is eliminated, and memory access conflicts in the loop execution process are reduced.

Description

technical field [0001] The present application relates to the field of coarse-grained reconfigurable structure compilers, and in particular, relates to a loop transformation model aimed at maximizing effective data reuse of reconfigurable structures and a configuration file modification strategy used in the code generation phase. Background technique [0002] Coarse-Grained Reconfigurable Architecture (CGRA) is a new hardware architecture with higher energy efficiency. It is mainly used for hardware acceleration of computing-intensive applications, such as video processing and neural network operations. After research and investigation, it is found that the application execution time is mainly consumed in the core part of the program loop. Reference ADRES [1] model gives a typical CGRA structure, such as figure 1 shown. The compiler abstracts the core part of the program loop as a data flow graph (data flow graph, DFG), and maps it to different processing elements (proces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/41
CPCG06F8/41Y02D10/00
Inventor 绳伟光陈雨歌蒋剑飞景乃锋王琴毛志刚
Owner SHANGHAI JIAO TONG UNIV
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